Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHRN (4S)

Test 1: uops

Code:

  sqshrn v0.4h, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723126125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303722038425472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqshrn v0.4h, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372251100275295472510100100100001001000050042771600300183003730037282716287401010020010008200100083003730037111020110099100100100001004001117171161129648100001003003830038300383003830038
1020430037225110082295472510100100100001001000050042771601300183003730037282717287411010020010008200100083003730037111020110099100100100001000001117181161129647100001003003830038300383003830038
10204300372241100103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
10204300372250000529295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383008530038
10204300372250000166295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
1020430037224000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038
1020430037225009061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007102162229633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000000545295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006403162229629010000103003830038300383003830038
100243003722500000000166295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722400000000486295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000768295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000001006402162229629010000103003830038300383003830038
10024300372240000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000200006402162229629010000103003830038300383003830038
10024300372250000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000147295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000036402162229629010000103003830038300383003830038
100243003722500000000166295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000126295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000103295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003721100211091010100001000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqshrn v0.4h, v8.4s, #3
  sqshrn v1.4h, v8.4s, #3
  sqshrn v2.4h, v8.4s, #3
  sqshrn v3.4h, v8.4s, #3
  sqshrn v4.4h, v8.4s, #3
  sqshrn v5.4h, v8.4s, #3
  sqshrn v6.4h, v8.4s, #3
  sqshrn v7.4h, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601501230258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391502130258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391502130258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391501272258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150330258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200941501230258010810080116100800205006401320200200200392003999776999080228200800322008003220039201012180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391503930258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
802042003915045630258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
802042003915032430258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000311151180160020036800001002004020040200402004020040
802042003915050430258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000105020212216212120036080000102004020040200402004020040
8002420039149004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000105020182216212120036080000102004020091200402004020040
8002420039150088402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010502018191692120036080000102004020040200402004020040
800242003915000402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010502015211692120036080000102004020040200402004020040
80024200391500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001050201591621920036080000102004020040200402004020040
8002420039150004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000105020182116212120036080000102004020040200402004020040
8002420039150150294258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001050201821162121200362080000102004020040200402004020040
800242003915000402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010502018211621920036080000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000208000020039200391180021109101080000105020182116212120036080000102004020040200402004020040
8002420039150004025800101080000108000050640000120020020039200399996310019800102080000208000020039200391180021109101080000105020182116211020036080000102004020040200402004020040