Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHRUN (S)

Test 1: uops

Code:

  sqshrun h0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100070073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000001873216222629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqshrun h0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000103295472510100100100001001000050042771600300183003730037282711028739101002001000820010008300373003711102011009910010010000100012783011171801600296450100001003003830038300383003830038
1020430037225012016629547251010010810024100100005004277160030018300373003728271628741101002001000820010008300373003711102011009910010010000100210211171701600296450100001003003830038300383003830038
10204300372250006129526251010012510000100100005344277160030054300853023028264328745102712001016820010166302793013611102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011711296330100001003003830038300383003830038
10204300372240006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296332100001003003830181300383003830038
10204300372250006129547991014010010040126106006544279864130018300373003728271328744101252001000020010000300373003711102011009910010010000100000000071211611296330100001003003830038300383003830038
102043003722509906129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071411611296330100001003003830038300383003830038
10204300372250006129547441010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003008030038300383003830038
102043003722503906129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000039982950280100451310024131075056428121603019830178301792830925288441061222106502210330301813022741100211091010100001020301011063007304242229629010000103003830038302733003830038
100243003722500011505233295022091009623100401211500814286624030342305103051228326472895511513201164422116253022430507121100211091010100001002200227990408763162329629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000010529547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372240000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006682162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006403162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000004400016402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504278512130270304173027528318392893410310261147324104853046130417101100211091010100001004301025405208082962229953310000103041830416304153041730416

Test 3: throughput

Count: 8

Code:

  sqshrun h0, s8, #3
  sqshrun h1, s8, #3
  sqshrun h2, s8, #3
  sqshrun h3, s8, #3
  sqshrun h4, s8, #3
  sqshrun h5, s8, #3
  sqshrun h6, s8, #3
  sqshrun h7, s8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049150000001206952580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183160200360800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160200360800001002004020040200402004020040
8020420039150000001206069980603102805061008054450064346412026620238202451001523100958053220080446202804472025220249518020110099100100800001000011895211151870670202361800001002030020294203042024320243
802042029915110044111926485011580599102805011018054751164421612022520141202951002428100938065020080539202805522029920286618020110099100100800001000000011151180161202430800001002029220301202502031120040
80204200391500000000952580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000411151180160200360800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160200360800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160200360800001002004020040200402004020040
80204200391500000090302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160200360800001002004020040200402004020040
802042003915000000330302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160200360800001002004020040200402004020040
80204200391500000060302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000010011151180160200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150574051800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050201316952003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020616992003680000102004020040200402004020040
80024200391502704025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050205164142003680000102004020040200402004020040
800242003915008425800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050205161392003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050201116842003680000102004020040200402004020040
8002420039150184025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050201216892003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050208161182003680000102004020040200402004020040
8002420039150498402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020916942003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020916842003680000102004020040200402004020040
8002420039150274025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050209161042003680000102004020040200402004020040