Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSUB (scalar, B)

Test 1: uops

Code:

  sqsub b0, b0, b1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037280024612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230027612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220048612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723009612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723009612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230012612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230024612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqsub b0, b0, b1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101160112963400100001003003830038300383003830038
10204300372250000008229548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101160112963400100001003003830038300383003830038
10204300372250000006129548251010010010000100100005964277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000307101160112963400100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101160112963400100001003003830038300383003830038
102043003722500000061295481231017613610040141101495004280027130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101160112963400100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101160112963400100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000008471160112963400100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000017707101160112963400100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000001507101160112963400100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000011107101160112963402100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250001206129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630010000103003830038300383003830038
1002430037225000006129548251001012100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010010006402162229630010000103003830038300383003830038
1002430037224011132010329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630010000103003830038300383003830038
10024300372250006010329548251001010100001010000504278670130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630110000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630010000103003830038300383003830038
100243003722500012010329548251001010100001010000504277313130018300373003728287328767100102010000202000030085300371110021109100101000010010306402162229630010000103003830038300383003830038
1002430037247000008229548631002010100001010000504277313130090300373003728294328767101602010163202000030037300371110021109100101000010000006402162329668010000103003830038300383003830038
100243003722500001086129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109100101000010000006402162229630010000103003830038300383003830038
100243003722500400103295482510010101000010101495042786701300183003730037282873287671001020100002020000300373003711100211091001010000100101206402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqsub b0, b1, b0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000094329548251010010010000100100005004277313030018030037300372829132874510100200100002002000030037300371110201100991001001000010047187102161129634100001003003830038300383003830038
102043003722500000251295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100907101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001004507101161129634100001003003830038300383003830038
1020430037224000006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010045817101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001003607101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001004337101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001004707101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001003367101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001004407101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001004307101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100012640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010003640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100093640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010200640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100415640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000120640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100543640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000177640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000186640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010005553640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqsub b0, b8, b9
  sqsub b1, b8, b9
  sqsub b2, b8, b9
  sqsub b3, b8, b9
  sqsub b4, b8, b9
  sqsub b5, b8, b9
  sqsub b6, b8, b9
  sqsub b7, b8, b9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150000000041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100029005110316112003620800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000206511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000100511011611200360800001002004020040200402004020040
802042003915000000004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010004103511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000100511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000000003262580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011612200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03183f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050201616121220036080000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000101005020121613820036080000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000650201216111220036080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020131681320036080000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010290050201116131320036280000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100095020816121320036080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020121611820036080000102004020040200402004020040
80024200391500530258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001010050201216121320036080000102004020040200402004020040
800242003914904025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000101005020121611720036080000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050201216121420036080000102004020040200402004020040