Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSUB (scalar, D)

Test 1: uops

Code:

  sqsub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037236125482510001000100039831330183037303724153289510001000200030373037111001100001273116112630100030383038303830383086
1004303723612548251000100010003983133018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
1004303722612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037226125482510001000100039831330183037303724153289510001000200030373037111001100001573116112630100030383038303830383038
1004303723612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqsub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225082295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372250189295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372250145295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372250103295484510112109100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
1020430037225084295482510100100100001001000050042773131300183003730037282930328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372240145295482510100100100001001000050042773130300183003730083282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372250145295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
1020430037225082295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611296340100001003003830038300383003830038
10204300372250498295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100071011611297040100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640516222963010000103003830038300383003830038
100243003722500000010229548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000006129548421001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000668216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010200640216222963010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010330646216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830082
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqsub d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000001932954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296349100001003003830038300383003830038
1020430037225000001472954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225000001032954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225110001119295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
100243003722500000726295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
100243003722500000504295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
100243003722500000536295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqsub d0, d8, d9
  sqsub d1, d8, d9
  sqsub d2, d8, d9
  sqsub d3, d8, d9
  sqsub d4, d8, d9
  sqsub d5, d8, d9
  sqsub d6, d8, d9
  sqsub d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500000630041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511021611200360800001002004020040200402004020040
802042003915000003540041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511021611200360800001002004020040200402004020040
802042003915000004260041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000516311611200360800001002004020040200402004020040
8020420039150000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000212258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
802042003915000003060041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000200000511011611200360800001002004020040200402004020040
80204200391500000180041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
8020420039150000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
8020420039150000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
8020420039150000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000001000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d2d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500402580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001050200011166101120036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200013160111020198280000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200012162111120036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200012160101120036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200011162111120036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050205014162131220036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200012160121320156080000102004020040200402004020040
80024200391500402580010108000010801055064000010200202003920146999631001980010208000020160000200392003911800211091010800001050205012162111020036080000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050205011160101020036080000102004020040200402004020040
80024200391500432580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001050200010162111120036080000102004020040200402004020040