Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSUB (vector, 16B)

Test 1: uops

Code:

  sqsub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722000006125482510001000100039831330183037303724153289511491000200030373037111001100000073116112630100030383038303830383038
1004303723000066125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230000126125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723000006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230000061254825100010001000398313301830373037241532895100010002000303730371110011000110073116112630100030383038303830383038
1004303722000006125482510001000100039831330183037303724153289510001000200030373037111001100000105373116112630100030383038303830383038
1004303722000006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723000006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722000006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722000006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqsub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007103161129634100001003003830038300383003830038
1020430037225001892954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003008530038300383003830038
102043003722400612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722509612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722510822954843101461231000010010000500427731330090030085300842826503287451010020010000200200003008430085211020110099100100100001002007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018330037300372826503287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006406166629630010000103003830038300383003830038
1002430037224000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006405165629630010000103003830038300383003830038
10024300372250000000004412954825100101010000101000050427731313001830082300372828732876710010201000020200003003730037111002110910101000010000000006406165629630010000103003830038300383003830038
10024300372250000000001162954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006406166529630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006405164429630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006405165629630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006406166429630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006406166529630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006405166529630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006405166529630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqsub v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372259612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830086300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100081007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100093007101161129634100001003003830038300383007130038
102043003722508229548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100390007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010073207101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100340007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003721102011009910010010000100350007101161129634100001003003830038300383003830038
102043003722506129548441010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100363007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001111029863842800270300543013330133282727287631026320410168202203343008430085211020110099100100100001000288207321251129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282652128745101002001000020020000300373003711102011009910010010000100021007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010066402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100186402162229697010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001041296402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010036402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010036402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100576402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010036402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201016220200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250000053629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100246402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqsub v0.16b, v8.16b, v9.16b
  sqsub v1.16b, v8.16b, v9.16b
  sqsub v2.16b, v8.16b, v9.16b
  sqsub v3.16b, v8.16b, v9.16b
  sqsub v4.16b, v8.16b, v9.16b
  sqsub v5.16b, v8.16b, v9.16b
  sqsub v6.16b, v8.16b, v9.16b
  sqsub v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010040051102161220036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100510051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100024051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100015051101161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010069051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003921802011009910010080000100024051101161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010038141051101161120036800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039998839997801002008000020016000020039200391180201100991001008000010003051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150004025800121080000108000050640000012002020039200399996310019800102080000201600002003920039118002110910108000010024165502000011600011200360080000102004020040200402004020040
80024200391500070525800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010020502000011600011200360080000102004020040200402004020040
80024200391500040258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100150502000011600011200360080000102004020040200402004020040
8002420039150004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010000502000011600011200360080000102004020040200402004020040
80024200391500040258001210800001080000506400000020020200392003999963100198001020800002016000020039200392180021109101080000100179502000011600011200360080000102004020040200402004020040
8002420039150004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010100502000011600011200360080000102004020040200402004020040
8002420039150004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010020502000011600011200360080000102004020040200402004020040
80024200391500040258001210800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100305020000116000112003615080000102004020040200402004020040
8002420039150004025800121080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010030502200011620111200360080000102004020040200402004020040
8002420039150004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010040502000011600011200360080000102004020040200402004020040