Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTN2 (4S)

Test 1: uops

Code:

  sqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723018015625482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372202106125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372202106125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000907262954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100200071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100103071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100100071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006629548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000035066402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162129630010000103003830038300383003830038
100243003722500000007262954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000036402162229630010000103003830038300383003830038
100243008422500000006129548831001010100001010000504277313030018030037300372828732876710010201000022200003003730037111002110910101000010000032006402162229630010000103003830038300383003830038
100243003722500000005362954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000003006402162229630010000103003830038300383003830038
100243003722500000001562954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000003006402162229630010000103003830038300383003830038
100243003722500000006312954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000001006402162229699010000103003830038300383003830038
100243003722400000002922954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000001036402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000003006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000002006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqxtn2 v0.8h, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000061295472510100100100001001000050042771603001830037300372827162874010100200100082002001630037300371110201100991001001000010000001117181160029646100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771603001830037300372827172874010100200100082002001630037300371110201100991001001000010000001117170160029646100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771603001830037300372827162874010100200100082002001630037300371110201100991001001000010000001117180160029646100001003003830038300383003830038
10204300372250000094295472510100100100001001000050042771603001830037300372827172874110100200100082002001630037300371110201100991001001000010000001117170160029645100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
10204300372250000197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
10204300852250000197295472510100100100001001000050042771603001830037300842825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
10204300372250000197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
10204300372240000197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
10204300372250000197295472510100100100001001000050042771603001830037300372827162874110100200100082002001630037300371110201100991001001000010000001117170160029646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722511026829547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100364411161052962910000103003830038300383003830038
1002430037225110268295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000644101610102962910000103003830038300383003830038
100243003722511026829547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100064481610102962910000103003830038300383003830038
1002430037224110268295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000644101610112962910000103003830038300383003830038
100243003722411026829547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000101064410165102962910000103003830038300383003830038
1002430037225110268295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001010644111612102962910000103003830038300383003830038
1002430037225110268295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000644101610112962910000103003830038300383003830038
1002430037225110268295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000644101610102962910000103003830038300383003830038
100243003722511026829547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100064451610102962910000103003830038300383003830038
1002430037225110268295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001041364411161082962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtn2 v0.8h, v8.4s
  movi v1.16b, 0
  sqxtn2 v1.8h, v8.4s
  movi v2.16b, 0
  sqxtn2 v2.8h, v8.4s
  movi v3.16b, 0
  sqxtn2 v3.8h, v8.4s
  movi v4.16b, 0
  sqxtn2 v4.8h, v8.4s
  movi v5.16b, 0
  sqxtn2 v5.8h, v8.4s
  movi v6.16b, 0
  sqxtn2 v6.8h, v8.4s
  movi v7.16b, 0
  sqxtn2 v7.8h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420077150000007125801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127081683200621600001002006620066200662006620066
16020420065151000002925801161008001610080028500640196015200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127591638200621600001002006620066200662006620066
16020420065151000002925801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127091686200621600001002006620066200662006620066
1602042006515000061325225801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127051687200621600001002006620066200662006620066
16020420065150000002925801161008001610080028500640196000200453200652006561280128200800282001600562006520065111602011009910010016000010000000011110127081688200621600001002006620066200662006620066
16020420065150000009425801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127031679200621600001002006620066200662006620066
16020420065150000007125801161008001610080028500640196115200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127031698200621600001002006620066200662006620066
16020420065150000002925801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110126081683200621600001002006620066200662006620066
16020420065150000002925801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110127081687200621600001002006620066200662006620066
160204200651500000011325801161008001610080028500640196000200450200652006561280128200800282001600562006520065111602011009910010016000010000000911110126081688200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200701503002009325800101080000108000050640000100200272004620046322800102080000201600002004620046111600211091010160000102412010048612262021122232004315160000102004720047200512004720051
16002420046150100101563258001010800001080000506400001002002720046200463228001020800002016000020046200461116002110910101600001010010046311262021123262004715160000102004720047200472004720047
160024200461501001001242580010108000010800005064000010020027200462004632280010208000020160000200502004611160021109101016000010296010040311222042217252004315160000102004720047200472004720047
1600242004615120010057258001010800001080000506400001002002720046200463228001020800002016000020046200461116002110910101600001000010046311222021121222004315160000102005120051200472004720051
1600242005015000020051258001010800001080000506400001052002720046200463228001020800002016000020046200461116002110910101600001000010045851222021123222004315160000102004720126201282005120047
1600242005015010020051258001010800001080000506400001052002720046200463228001020800002016000020046200461116002110910101600001000010045351252021122232004315160000102005120051200472004720047
1600242005015010010057258001010800001080000506400001052002720046200463228001020800002016000020113200571116002110910101600001023010046351232021123232004315160000102004720047200472004720047
16002420046151100000512580010108000010800005064000010020027200502005032280010208000020160000200502005011160021109101016000010000100501162162421123222004330160000102005120051200512004720051
1600242005015020010057258001010800001080000506400001002002720046200463228001020800002016000020046200461116002110910101600001000010045311222121122212004315160000102004720047200472004720047
16002420046150100100512580010108000010800005064000010020027200462004632280010208000020160000200462004611160021109101016000010200010045351242021124222004315160000102004720047200472004720051

Test 5: throughput

Count: 16

Code:

  sqxtn2 v0.8h, v16.4s
  sqxtn2 v1.8h, v16.4s
  sqxtn2 v2.8h, v16.4s
  sqxtn2 v3.8h, v16.4s
  sqxtn2 v4.8h, v16.4s
  sqxtn2 v5.8h, v16.4s
  sqxtn2 v6.8h, v16.4s
  sqxtn2 v7.8h, v16.4s
  sqxtn2 v8.8h, v16.4s
  sqxtn2 v9.8h, v16.4s
  sqxtn2 v10.8h, v16.4s
  sqxtn2 v11.8h, v16.4s
  sqxtn2 v12.8h, v16.4s
  sqxtn2 v13.8h, v16.4s
  sqxtn2 v14.8h, v16.4s
  sqxtn2 v15.8h, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400493000200251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400393000378251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001001031111011801600400361600001004004040040400404004040040
160204400393000198251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400393000114251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400392990179251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600285001280196040029400494004919976919986160128200160038200320076400484004811160201100991001001600001000002221012912311400461600001004004940049400504004940049
16020440048300064261601161001600161001600285001280196040029400484004819976919986160128200160038200320076400484004911160201100991001001600001001002221012912311400461600001004004940049400494004940050
16020440048300064271601161001600161001600285001280196040029400484004919976919986160128200160038200320076400494004811160201100991001001600001000002221012912312400461600001004005040049400494004940050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)09l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005130001001627251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002333103916111212540036165160000104004040040400404004040040
160024400393001100099251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002433111916111271640036165160000104004040040400404004040040
1600244003930011000992516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001001501002233102516111212540036165160000104008940040400404004040040
160024400392991100099251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600221091010160000100001002333112616111282840036165160000104004040040400404004040040
1600244003930011000183251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039211600211091010160000100001002433112716111252540036155160000104004040040400404004040040
160024400393001100193251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002333112016111271640036165160000104004040040400404004040040
160024400393001100099251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002433112816111232740036165160000104004040040400404004040040
160024400393001100193251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002433112616111262640036165160000104004040040400404004040040
1600244003930011001187251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100001002433111816111261640242165160000104004040040400404004040040
160024400913001104051705251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100011002433112616111252540036165160000104004040040400404004040040