Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTN2 (8H)

Test 1: uops

Code:

  sqxtn2 v0.16b, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372201032548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372302102548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372301032548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqxtn2 v0.16b, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225001032954825101001001000010010000500427731303001830037300372826503287451010020010164200200003003730037111020110099100100100001000071021611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372254140612954825101001001000010010000500427731303001830037300372826503287631010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001056402162229630010000103003830038300383003830038
1002430037225000712954825100101010000101000050427731303001830037300372828726287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006401162229630010000103003830038300383003830038
100243008322500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqxtn2 v0.16b, v0.8h
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500600612954725101001001000010010000500427716013001830037300372827106287411010020010008200200163003730037111020110099100100100001000001117170160029645100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372827106287401010020010008200200163003730037111020110099100100100001000001117170160129646100001003003830038300383003830038
102043003722510000612954725101001001000010010000500427851213001830037300372825206287331010020010000200200003003730037111020110099100100100001000031117170160029646100001003003830038300383003830038
1020430037227001098001032954725101001001000010010000500427716013001830037300372827106287411010020010008200200163003730037111020110099100100100001000201117170160029645100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372827107287401010020010008200200163003730037111020110099100100100001000001117180160029645100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716003001830037300372827107287411010020010008200200163003730037111020110099100100100001000001117170160030034100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372827106287401010020010008200200163003730037111020110099100100100001000001117170160029645100001003003830038300383003830038
102043003722500300001982954725101001001000010010000500427716013001830037300372827106287411010020010008200200163003730037111020110099100100100001000001117170160029645100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716003001830037300372827106287401010020010008200200163003730037111020110099100100100001000001117170160029645100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372827106287401010020010008200200163003730037111020110099100100100001000001117180160029646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300842250061295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830084
10024300372250061295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006400216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtn2 v0.16b, v8.8h
  movi v1.16b, 0
  sqxtn2 v1.16b, v8.8h
  movi v2.16b, 0
  sqxtn2 v2.16b, v8.8h
  movi v3.16b, 0
  sqxtn2 v3.16b, v8.8h
  movi v4.16b, 0
  sqxtn2 v4.16b, v8.8h
  movi v5.16b, 0
  sqxtn2 v5.16b, v8.8h
  movi v6.16b, 0
  sqxtn2 v6.16b, v8.8h
  movi v7.16b, 0
  sqxtn2 v7.16b, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915100000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
16020420065150000036029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
1602042006515000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000123011110119016002006201600001002006620066201322006620066
1602042006515110000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
1602042006515000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000156011110119016002006201600001002006620066200662006620066
16020420065150000000124258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
1602042006515000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066
1602042006515001000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000000011110119016002006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200711500000452580010108000010800005064000001520031200462004632280010208000020160000200502005011160021109101016000010000100301641624421342004330160000102004720051200512005120051
1600242005515000005125800101080000108000050640000011020031200502004632280010208000020160000200502005011160021109101016000010000100271351320211442004315160000102004720047200472004720047
1600242005415000004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010010100261361320211342004315160000102004720047200472004720047
1600242005415000004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010310100271351420211432004315160000102004720047200472004720047
16002420054150000051258001010800001080000506400000110200312004620050322800102080000201600002005020050111600211091010160000100063100271352320211442004715160000102004720047200472004720047
1600242005415000004525800101080000108000050640000011020027200462004632280010208000020160000200462004611160021109101016000010009100261361420222342004315160000102004720047200472004720047
16002420054150000045258001010800001080000506400001110200272004620046322800102080000201600002004620046111600211091010160000100084100271351420211442004315160000102004720047200472004720047
1600242005815000004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010009100271351420211432004315160000102004720047200472004720047
1600242005415000004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010000100271362424222442004715160000102005120051200512021320267
1600242029915212396884525800101080000108000050640000011020031200502005032280010208000020160000200502005011160021109101016000010000100261351420211442004315160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  sqxtn2 v0.16b, v16.8h
  sqxtn2 v1.16b, v16.8h
  sqxtn2 v2.16b, v16.8h
  sqxtn2 v3.16b, v16.8h
  sqxtn2 v4.16b, v16.8h
  sqxtn2 v5.16b, v16.8h
  sqxtn2 v6.16b, v16.8h
  sqxtn2 v7.16b, v16.8h
  sqxtn2 v8.16b, v16.8h
  sqxtn2 v9.16b, v16.8h
  sqxtn2 v10.16b, v16.8h
  sqxtn2 v11.16b, v16.8h
  sqxtn2 v12.16b, v16.8h
  sqxtn2 v13.16b, v16.8h
  sqxtn2 v14.16b, v16.8h
  sqxtn2 v15.16b, v16.8h
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440058300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000031111011811600400361600001004004040040400404004040040
1602044003930000012030251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000031001111011801600400361600001004004040040400404004040040
160204400393000000072251601081001600081001600205001280132140020400394003919977619990160120200160032200320064402444003911160201100991001001600001000043001111011801600400361600001004004040040400404004040040
160204400393000000051251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000056001111011801602400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000031111011801600400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100001091111011801600400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000031111011801600400361600001004004040040400404004040040
160204400393000000069525160108119160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011801600400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100020061111011801600400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100001091111011801600400361600001004004040040400404014240040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400513000000463016001010160000101600005012800001154002040039400391999603200191600102016000020320000400394003911160021109101016000010200000100228115162117740036155160000104004040040400404004040040
160024400393000000462916001010160000101600005012800001154002040039400391999603200191600102016000020320000400394003911160021109101016000010800010100228417162226440036155160000104004040040400404004040040
1600244003930000004627160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000105303000100228516162114740036155160000104004040040400404004040040
1600244003930000004626160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000101006000100228414162114740036155160000104004040040400404004040040
160024400393000000462616001010160000101600005012800001154002040039400891999603200191600102016000020320000400394003911160021109101016000010700000100228413162117640036155160000104004040040400404004040040
160024400392990000462816001010160000101600005012800001154002040039400391999603200191600102016000020320000400394003911160021109101016000010400000100228416162116740036155160000104004040040400404004040040
16002440039300000046261600101016000010160000501280000115400204003940039199960320019160010201600002032000040039400391116002110910101600001011090001002211416162213440036155160000104004040040400404004040040
160024400393000000462716001010160000101600005012800001154002040039400391999603200191600102016000020320000400394003911160021109101016000010109000100228414162116440036155160000104004040040400404004040040
1600244003930000004626160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000102600000100228414162114340036155160000104004040040400404004040040
160024400393000000462616001010160000101600005012800001154002040039400391999603200191600102016000020320000400394003911160021109101016000010600000100228414162117640036155160000104004040040400404004040040