Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTN (4S)

Test 1: uops

Code:

  sqxtn v0.4h, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722264251254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004308522061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037211001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqxtn v0.4h, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000001506129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000073521611296330100001003003830038300383003830038
102043003722400000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830086
102043003722400000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000100000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000103000071011611296330100001003003830038300383008130038
1020430037225000003906129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000012829538251004510100081010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372240000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277634130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqxtn v0.4h, v8.4s
  sqxtn v1.4h, v8.4s
  sqxtn v2.4h, v8.4s
  sqxtn v3.4h, v8.4s
  sqxtn v4.4h, v8.4s
  sqxtn v5.4h, v8.4s
  sqxtn v6.4h, v8.4s
  sqxtn v7.4h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581510000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000200011151180160020036800001002004020040200402004020040
80204200391500009264302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000002606011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000000211151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000300011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000100011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000000011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000100011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401962002020039200399977699908012020080032200800322003920039118020110099100100800001000000000011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000100011151180160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000000011151180160020077800001002004020040200402004020092

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000050200111612122003680000102004020040200402004020040
80024200391500402580010108009910800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100200050200131613122003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000012050200121614132003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000120050200111612132003680000102004020040200402004020040
8002420039150061258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000123050200131613132003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100010050200131613112003680000102004020040200402004020040
80024200391500402580107108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100010050200111613122003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100006050200121613102003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000256050200121611112003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100020050200121613132003680000102004020040200402004020040