Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTN (S)

Test 1: uops

Code:

  sqxtn h0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300126125472510001000100039816030183037303724143289510001000100030373037111001100000073216112629100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007873116112629100030383038303830383038
100430372200061254725100010001000398160301830373037241432895100010001000303730371110011000004573116112629100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000002794116112629100030383038303830383038
100430372200061254725100010001000398160301830373037241432895100010001000303730371110011000001273116112629100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000004573116112629100030383038303830383038
10043037220006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730841110011000602773116112629100030383038303830383038
1004303723000160254725100010001000398160301830373037241432895100010001000303730371110011000005773116112629100030383038303830383038
100430372200061254725100010001000398160301830373037241432895100010001000303730371110011000003073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqxtn h0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000010071011611296330100001003003830038300383003830038
10204300842250000011342954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001803003730037282923287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000002512954725101001001000012610000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000008262954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000005742954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372250000019412954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383008630038
1020430037225000009042954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000009662954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000000046829547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000000034429547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000000407295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001001048640216222962910000103003830038300383003830038
10024300372250000000040829547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000100053329547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830085
10024300372250000000045529547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000000041129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372240000000049829547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100100640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqxtn h0, s8
  sqxtn h1, s8
  sqxtn h2, s8
  sqxtn h3, s8
  sqxtn h4, s8
  sqxtn h5, s8
  sqxtn h6, s8
  sqxtn h7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061150010302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151183164520036800001002004020040200402004020040
8020420039150110302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185164520036800001002004020040200402004020040
8020420039150110952580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185164520036800001002004020040200402004020040
8020420039150110302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151183164420036800001002004020040200402004020040
80204200391501102042580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010010011151184164520036800001002004020040200402004020040
8020420039150110302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010010011151185165520036800001002004020040200402004020040
8020420039150110952580108100800081008002052464013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185165420036800001002004020040200402004020040
802042003915011011162580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185165420036800001002010020040200402004020040
8020420039150110302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185164520036800001002004020040200402004020040
8020420039150110302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000011151185165420036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150000057325800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416322003680000102004020040200402004020040
800242003915000004025800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000101005020416442003680000102004020040200402004020040
8002420039150100012425800101080000108000050640000012002020039200399996310019800102080000208000020088200391180021109101080000100005020416442003680000102004020040200402004020040
80024200391500000119425800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000100005020316342003680000102004020040200402004020040
8002420039150000066325800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000104414405020416442003680000102004020040200402004020040
800242003915000004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416442003680000102004020040200402004020040
800242003915000004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100005020416442003680000102004020040200402004020040
80024200391500001084025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100005020316442003680000102004020040200402004020040
800242003915000004025800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000100005020416332003680000102004020040200402004020040
8002420039150000099425800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100005020316452003680000102004020040200402004020040