Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTUN2 (2D)

Test 1: uops

Code:

  sqxtun2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
1004303722061254844100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100070073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqxtun2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000009061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000001571011611296340100001003003830038300383003830038
102043003722500000004412954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000013271011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300852826532874510100200100002002000030037300371110201100991001001000010000011171011611296340100001003003830038300383003830038
102043003722500000007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000012071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000012371011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000013571011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000001571011611296340100001003003830038300383003830038
10204300372250010090612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030087300371110201100991001001000010000010571011611296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000011171011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010001176403164429630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183008430037282923287671001020100002020000300373003711100211091010100001000876404164429630010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006404164429630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010001056403163429630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010001086404164429630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100706403164429630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010001206404164429630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010001116404164329630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006404163429630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006403164429630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqxtun2 v0.4s, v0.2d
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000061295472510100100100001161000050042771603001830037300372827172874010100200100082002001630037300371110201100991001001000010000330511117181629646100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160300183003730037282717287411010020010008200200163003730037111020110099100100100001000000151117171629646100001003003830038300383003830038
102043003722400000612954725101001131000010010000500427716030018300373003728271628740101002001000820020016300373022811102011009910010010000100000091117181629645100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771603001830037300372827162874110100200100082002001630037300371110201100991001001000010000350151117181629646100001003003830038300383003830038
10204301812240001207612954725101001001000010210150500427716030054300373003728271628776105582001000820420016300373003711102011009910010010000100000091117171629646100001003003830038300383003830038
102043003722400101048429538251010010010000100100005004277160300183003730037282716287411010020010008200200163003730037111020110099100100100001000000121117171629645100001003003830038300383003830038
1020430037225000006129547251010010010000103101505004277160300183003730037282716287411010020010008200200163003730037111020110099100100100001000020151117171629645100001003003830038300383003830038
10204300372250001206129547251010010010000100100005004277160300183003730037282716287411010020010008200200163003730037111020110099100100100001000000121117171629645100001003008530038300383003830038
10204300372250000044129547251010010010000100100005004277160300183003730037282717287401010020010179200200163003730037111020110099100100100001000010112261117181629804100001003003830038300383003830038
10204300852250003108612954725101001001000010010000500427716030018300373003728271728741102522001000820020016300373008411102011009910010010000100014001117171629646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100900640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100900640316332962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002020000300373003711100211091010100001001110640316332962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183008430084282863287671001020100002020000300373003711100211091010100001001050640316332962910000103003830038300383003830038
100243003722400612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100960640316332962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002020000300373003711100211091010100001001050640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100840640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100960640316332962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002020000300373003711100211091010100001001170640316332962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002020000300373003711100211091010100001001170640316332962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtun2 v0.4s, v8.2d
  movi v1.16b, 0
  sqxtun2 v1.4s, v8.2d
  movi v2.16b, 0
  sqxtun2 v2.4s, v8.2d
  movi v3.16b, 0
  sqxtun2 v3.4s, v8.2d
  movi v4.16b, 0
  sqxtun2 v4.4s, v8.2d
  movi v5.16b, 0
  sqxtun2 v5.4s, v8.2d
  movi v6.16b, 0
  sqxtun2 v6.4s, v8.2d
  movi v7.16b, 0
  sqxtun2 v7.4s, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200651500000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001001601111011901600200621600001002006620066200662006620066
16020420065150000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100031111011901600200621600001002006620066200662006620066
16020420065151000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100401111011901600200621600001002006620066200662006620066
16020420065150000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100031111011901600200621600001002006620066200662006620066
16020420065151000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100301111011901600200621600001002006620066200662006620066
160204200651500000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000601111011901600200621600001002006620066200662006620066
16020420065151000929258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100301111011901600200621600001002006620066200662006620066
16020420065150000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011901600200621600001002006620066200662006620066
16020420065151000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100501111011901600200621600001002006620066200662006620066
16020420065150000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100031111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200691500045258001010800001080000506400000102002720046200463228001020800002016000020046200461116002110910101600001090010026811320211232004315160000102004720047200472004720055
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200501116002110910101600001000010025841320411322004315160000102004720047200472004720067
1600242004615000452580010108000010800005064000001520027200462005032280010208000020160000200462004611160021109101016000010000100258413149211332004315160000102004720047200472004720055
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010026852320221322004315160000102004720047200472004720067
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001003010026841320211332004315160000102005120047200472004720067
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010026841220211332004315160000102004720047200472004720067
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010026841320211322004315160000102004720047200472004720055
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010026841320211322004315160000102004720047200472004720059
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001013110026841324211332004315160000102004720047200472004720059
160024200461500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010026841320211232004315160000102004720047200472004720063

Test 5: throughput

Count: 16

Code:

  sqxtun2 v0.4s, v16.2d
  sqxtun2 v1.4s, v16.2d
  sqxtun2 v2.4s, v16.2d
  sqxtun2 v3.4s, v16.2d
  sqxtun2 v4.4s, v16.2d
  sqxtun2 v5.4s, v16.2d
  sqxtun2 v6.4s, v16.2d
  sqxtun2 v7.4s, v16.2d
  sqxtun2 v8.4s, v16.2d
  sqxtun2 v9.4s, v16.2d
  sqxtun2 v10.4s, v16.2d
  sqxtun2 v11.4s, v16.2d
  sqxtun2 v12.4s, v16.2d
  sqxtun2 v13.4s, v16.2d
  sqxtun2 v14.4s, v16.2d
  sqxtun2 v15.4s, v16.2d
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440058299000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001001001111011801601400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013204002004003940039199776199901601202001600322003200644003940039111602011009910010016000010011801111011801600400361600001004004040040400404004040100
160204400393000003025160108100160008100160020500128013204002004003940039199776199901601202001600322003200644003940039111602011009910010016000010025301111011821611400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001002001111011801601400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001001001111011811601400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001002001111011801601400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013204002004003940039199776199901601202001600322003200644003940039111602011009910010016000010019301111011801610400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001001001111011801611400361600001004004040040400404004040040
16020440039300000302516010810016000810016002050012801320400200400394003919977619990160120200160032200320064400394003911160201100991001001600001001001111011801601400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400393000046251600101016000010160000501280000104002040039400391999603200191600102016000020320000400394003911160021109101016000010020100246222716211252540036155160000104004040040400404006440040
16002440039300005225160010101600001016000050128000001400204003940039199960320019160010201600002032000040039400391116002110910101600001001861002462225164222525400363010160000104004040040400404008340040
160024400393003176942516001010160000101600005012800000140020400394003919996032001916011420160000203200004003940039111600211091010160000102191002462225164221325400363010160000104004040040400404008140040
16002440039300005225160010101600001016000050128000001400204003940039199960320019160010201600002032000040039400391116002110910101600001001791002462225164222525400363010160000104004040040400404007840040
16002440039300005225160010101600001016000050128000001400204003940039199960320019160010201600002032000040039400391116002110910101600001001861002462225164221325400363010160000104004040040400404007840040
16002440039300004625160010101600001016000050128000000400204003940039199960320019160010201600002032000040039400391116002110910101600001000165100223111316211251340036155160000104004040040400404007540040
1600244003930012071125160010101600001016000050128000011400204003940039199960320019160010201600002032000040039400391116002110910101600001002815100223112516211252540036155160000104004040040400404007540040
160025400392990046251600101016000010160000501280000114002040039400391999603200191600102016000020320000400394003911160021109101016000010020100223112516211132540036155160000104004040040400404008140040
160024400393000046251600101016000010160000501280000114002040039400391999603200191600102016000020320000400394003911160021109101016000010010100223112516211252540036155160000104004040040400404009440040
160024400393000046251600101016000010160000501280000114002040039400391999603200191600102016000020320000400394003911160021109101016000010010100223112516211251140036155160000104004040040400404008140040