Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTUN2 (4S)

Test 1: uops

Code:

  sqxtun2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073416112630100030383038303830383038
100430372306125482510001000100039831313018303730372415329191000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723027425482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000973116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqxtun2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225002646129548251010010010000100100005004277313030065300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
102043003722500010329548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
1020430037225001216829548251010010010000100100005004277313030018300373003728268328745102702001000020020000300373003711102011009910010010000100001200071021622296340100001003003830038300383003830038
1020430037224006136329548251010010410000120100005004277313030018300853003728265328745101002001000020020000300373003711102011009910010010000100000090071021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
1020430037225001263129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830086
1020430037225001446129548251010010010000100100005004277313130018300373003728269328745101002001000020020000300843003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373008128265328745101002001000020020000300373003711102011009910010010000100001030071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722501032954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722501052954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383008630038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
100243003722502122954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006403163329630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqxtun2 v0.8h, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250010329547251010010010000100100005004277160030018300373003728271728740101002001000820020000300373003711102011009910010010000100001117180160029645100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020430037225906129547251010010010024100100005004277160030018300373003728271728740101002001018020020016300373003711102011009910010010000100001117180160029646100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728271628741101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020430037224006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117180160029646100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160130018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037224006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010100640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771603001830037300372828632876710010201000020203223003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtun2 v0.8h, v8.4s
  movi v1.16b, 0
  sqxtun2 v1.8h, v8.4s
  movi v2.16b, 0
  sqxtun2 v2.8h, v8.4s
  movi v3.16b, 0
  sqxtun2 v3.8h, v8.4s
  movi v4.16b, 0
  sqxtun2 v4.8h, v8.4s
  movi v5.16b, 0
  sqxtun2 v5.8h, v8.4s
  movi v6.16b, 0
  sqxtun2 v6.8h, v8.4s
  movi v7.16b, 0
  sqxtun2 v7.8h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008815000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
16020420065151000694258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
16020420065150000831258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066
1602042006515100029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000011110119162006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242007115038745258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010030821192021116620043150160000102004720047200472004720047
16002420046151910822580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010001210030821720211161620043150160000102004720047200472004720047
16002420046150010162580010108000010800005064000011520031200462004632280010208000020160000200462004611160021109101016000010000100408211720211161620043150160000102004720047200472004720047
1600242004615107925800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100001003782115202111616200431578160000102004720047200472004720047
160024200461500710258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010040831122042116620043150160000102004720047200472004720047
16002420050150045258001010800001080000506400001152002720046200463228001020800002016000020050200501116002110910101600001000010040831172421161620043150160000102004720047200472004720047
160024200461500797258001010800001080000506400001152002720046200463228001020800002016000020050200501116002110910101600001010010043114272021117720043150160000102004720047200472004720047
16002420046150070425800101080000108000050640000115200272004620046322800102080000201600002005020050111600211091010160000100001004083152021161620043150160000102004720047200472004720047
1600242004615004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100001003083142021161620043150160000102004720047200472004720047
16002420046150045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010030821132021116620043150160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  sqxtun2 v0.8h, v16.4s
  sqxtun2 v1.8h, v16.4s
  sqxtun2 v2.8h, v16.4s
  sqxtun2 v3.8h, v16.4s
  sqxtun2 v4.8h, v16.4s
  sqxtun2 v5.8h, v16.4s
  sqxtun2 v6.8h, v16.4s
  sqxtun2 v7.8h, v16.4s
  sqxtun2 v8.8h, v16.4s
  sqxtun2 v9.8h, v16.4s
  sqxtun2 v10.8h, v16.4s
  sqxtun2 v11.8h, v16.4s
  sqxtun2 v12.8h, v16.4s
  sqxtun2 v13.8h, v16.4s
  sqxtun2 v14.8h, v16.4s
  sqxtun2 v15.8h, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400593001203025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
160204400393003303025160108100160008100160020500128013214002004003940090199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
160204400393001208825160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
16020440039300303025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
160204400393003303025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400871600001004004040040400404004040040
1602044003930040203025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
16020440039299003025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
1602044003930023703025160108100160008100160020585128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
1602044003930030903025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040
160204400392996003025160108100160008100160020500128013214002004003940039199776199901601202001600322003200644003940039111602011009910010016000010000001111011801600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930000046251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010000001002462214164119640036155160000104004040040400404004040040
160024400393000005225160010101600001016000050128000001400200400394003919996320019160010201600002032000040039400391116002110910101600001000000100246228164229740036155160000104004040040400404004040040
16002440039300000462516001010160000101600005012800001140020040039400391999632001916001020160000203200004003940039111600211091010160000100000010024622516422415400361510160000104004040040400404004040040
16002440039300240046251600101016000010160000501280000114002004003940039199963200191601172016000020320000400394003911160021109101016000010000001002462191642275400363010160000104004040040400404004040040
1600244003930000046251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010000001002261161622191140036305160000104004040040400404004040040
160024400392990004625160010101600001016000050128000011400200400394003919979320019160010201600002032000040039400391116002110910101600001000000100223119162119640036155160000104004040040400404004040040
16002440039300180004625160010101600001016000050128000011400200400394003919978320019160010201600002032000040039400391116002110910101600001000000100223111016411101240036155160000104004040040400404004040040
160024400392992280046251600101016000010160000501280000114002004003940039199793200191600102016000020320000400394003911160021109101016000010000301002231151621191140036155160000104004040040400404004040040
1600244003930045004625160010101600001016000050128000001400200400394003919990320019160010201600002032000040039400391116002110910101600001000000100226119162118640036305160000104004040040400404004040040
160024400393002580046251600101016000010160000501280000114002004003940039199873200191600102016000020320000400394003911160021109101016000010002001002232191621161240036155160000104004040040400404004040040