Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTUN2 (8H)

Test 1: uops

Code:

  sqxtun2 v0.16b, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372201032548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073124112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqxtun2 v0.16b, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383008530038
1020430037225636129548251010010010000100100005114277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
102043003722596129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000114008229548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000276006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830419
10024304142281289366161458729485158100761410040191119271428681203030630413304182831642289121110420113162422618304133041491100211091010100001022013895008943807429947410000103040630417304133018030453
100243027422808992774815220295211781008014100641110894874288169030306304153046628320332893111206221130924226343041430413101100211091010100001040083350081151062229630010000103003830038300383003830038
1002430037224000309006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000210072629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250003210072629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000138006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000294006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqxtun2 v0.16b, v0.8h
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171801629646100001003003830038300383003830038
1020430037225012061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171701629645100001003003830038300383003830038
1020430037225060536295472510100100100001001000050042771601300183003730037282717287411010020010008200200163003730037111020110099100100100001000011171801629646100001003003830038300383003830038
1020430037225090103295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171801629645100001003003830038300383003830038
102043003722509082295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171811629645100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171801629646100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000011171701629646100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171801629645100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171801629646100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171701629646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954725100101410000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640416332962910000103003830038300383003830038
100243003722510612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225030612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
100243003722500612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038
1002430037225007262954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640316332962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtun2 v0.16b, v8.8h
  movi v1.16b, 0
  sqxtun2 v1.16b, v8.8h
  movi v2.16b, 0
  sqxtun2 v2.16b, v8.8h
  movi v3.16b, 0
  sqxtun2 v3.16b, v8.8h
  movi v4.16b, 0
  sqxtun2 v4.16b, v8.8h
  movi v5.16b, 0
  sqxtun2 v5.16b, v8.8h
  movi v6.16b, 0
  sqxtun2 v6.16b, v8.8h
  movi v7.16b, 0
  sqxtun2 v7.16b, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420088150101000289258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100001111011921611200621600001002006620066200662006620066
1602042006515010100029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100061111011911611200621600001002006620066200662006620066
1602042006515010100029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
1602042006515010100052258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111014611611200621600001002006620066200662006620066
1602042006515010100029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
16020420065150101000498258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011911611200621600001002006620132200662006620066
16020420065150101000504258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066
1602042006515010100092258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100101111011911611200621600001002006620066200662006620066
16020420065150101000155258011610080016100800285006401961200452006520065612801282008002820016005620065201321116020110099100100160000100001111011911611200621600001002006620066200662006620066
16020420065151101000113258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011911611200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200651510005525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010028811620211392004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010028841520211392004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462004694580010208000020160000200462004611160021109101016000010020010032841920211532004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010026841320211952004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010032841320211392004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010028841320211352004315160000102004720047200472004720047
16002420046150000136725800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010032841520211352004315160000102004720047200472004720047
160024200461500604525800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010028841920211742004315160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200270200462005032280010208000020160000200462004611160021109101016000010000010028841320211992004315160000102004720047200472004720047
160024200461500606625800101080000108000050640000115200270200462004632280010208000020160000200462004611160021109101016000010000010028841520211532004315160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  sqxtun2 v0.16b, v16.8h
  sqxtun2 v1.16b, v16.8h
  sqxtun2 v2.16b, v16.8h
  sqxtun2 v3.16b, v16.8h
  sqxtun2 v4.16b, v16.8h
  sqxtun2 v5.16b, v16.8h
  sqxtun2 v6.16b, v16.8h
  sqxtun2 v7.16b, v16.8h
  sqxtun2 v8.16b, v16.8h
  sqxtun2 v9.16b, v16.8h
  sqxtun2 v10.16b, v16.8h
  sqxtun2 v11.16b, v16.8h
  sqxtun2 v12.16b, v16.8h
  sqxtun2 v13.16b, v16.8h
  sqxtun2 v14.16b, v16.8h
  sqxtun2 v15.16b, v16.8h
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440058300000000135251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118316024003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016024003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016024003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016024003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000100011110118016024003601600001004004040040400404004040040
1602044003930000000051441602061001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016014003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016034003601600001004004040040400404004040040
1602044003929900000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016024003601600001004004040040400404004040040
16020440039299000000156251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000000011110118016024003601600001004004040040400404004040040
16020440039299000000201251601081001600081001600205001280132040020400394003919977061999016012020016003220032006440193400391116020110099100100160000100000000011110118016034003601600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400513001000882516001010160000101600005012800001004002040039400391999632001916001020160000203200004003940039111600211091010160000100030100228318162116440036206160000104004040040400404004040040
1600244003929910004625160010101600001016000050128000010040020400394003919996320019160010201600002032000040039400391116002110910101600001000001002283161621151040036206160000104004040040400404004040040
16002440039300002105052516001010160000101600005012800001004002040039400391999632001916001020160000203200004003940039111600211091010160000100147301002231181621151140036206160000104004040040400404004040040
16002440039299000015325160010101600001016000050128000010040020400394003919996320019160010201600002032000040039400391116002110910101600001001301002283141621110640036206160000104004040040400404004040040
16002440039300000019525160010101600001016000050128000010540020400394003919996320019160010201600002032000040039400391116002110910101600001023001003083161621141040036206160000104004040040400404004040040
16002440039300001235211125160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000001002231171621151240036206160000104004040040400404004040040
16002440039300000018025160010101600001016000050128000010040020400394003919996320019160010201600002032000040039400391116002210910101600001000001002233151621151040036206160000104004040040400404004040040
16002440039300000039025160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400395116002110910101600001000021002232110162116440036206160000104004040040402494004040040
16002440039300009015525160010101600001016000050128000010540020400394003919996320019160010201600002032000040039400391116002110910101600001000001002231141621110640036206160000104004040040400404004040040
1600244003930000006725160205101600001016000050128000010540020400394003919996320019160010201600002032000040039400391116002110910101600001003001002233151621151240036206160000104004040040400404004040040