Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRHADD (vector, 4H)

Test 1: uops

Code:

  srhadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110001073216111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
100420371508216872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  srhadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150015536196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002071011611197910100001002003820038200382003820038
10204200371500082196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979131100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002671011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001005071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000002306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444031876710010201000020200002003720037111002110910101000010000100006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003731100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000020006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000020006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  srhadd v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007102161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100013007101162119825100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422261874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200101802002000020037200371110201100991001001000010001007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100010640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100044144640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000203640217221978510000102003820038200382003820038
10024200371496119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100045978640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100010640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100003640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  srhadd v0.4h, v8.4h, v9.4h
  srhadd v1.4h, v8.4h, v9.4h
  srhadd v2.4h, v8.4h, v9.4h
  srhadd v3.4h, v8.4h, v9.4h
  srhadd v4.4h, v8.4h, v9.4h
  srhadd v5.4h, v8.4h, v9.4h
  srhadd v6.4h, v8.4h, v9.4h
  srhadd v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000100511031611200350800001002003920039200392003920039
802042003814900000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000106511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008011650064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000300511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000100511011611200350800001002003920039200392003920039
8020420038150000002302580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000403511011611200350800001002003920039200392003920039
8020420038150000008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000002503511021611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000103511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000106511011611200350800001002003920039200392003920039
8020420038151000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000003000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000023511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100030000502003160045200350080000102003920039200392003920039
80024200381500000102258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160034200350080000102003920039200392003920039
8002420038150000085258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160037200350080000102003920039200392003920039
80024200381500000718258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160024200350080000102003920039200392003920039
8002420038150000060258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160035200350080000102003920039200392003920039
8002420038150000085258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160033200350080000102003920039200392003920039
80024200381500000148258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502002160025200350080000102003920039200392003920039
8002420038150000083258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502002160024200350080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502003160026200350080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000000502004160043200350080000102003920039200392003920039