Firestorm: SRI (vector, 16B) measurements

Code:

  sri v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	1	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1077	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	26	3	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	23	7883	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1080	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	26	3	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	46	0	9	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	4	0	6	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10152	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	22	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	5933	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	7	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	5	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10024	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	6	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	27	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	124	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	1	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	6	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	126	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	150	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	429	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	0	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	15	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	2	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	536	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	84	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	126	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	126	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	745	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	470	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	24	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	1018	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	193	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	19	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	1186	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.16b, v8.16b, #3
  movi v1.16b, 0
  sri v1.16b, v8.16b, #3
  movi v2.16b, 0
  sri v2.16b, v8.16b, #3
  movi v3.16b, 0
  sri v3.16b, v8.16b, #3
  movi v4.16b, 0
  sri v4.16b, v8.16b, #3
  movi v5.16b, 0
  sri v5.16b, v8.16b, #3
  movi v6.16b, 0
  sri v6.16b, v8.16b, #3
  movi v7.16b, 0
  sri v7.16b, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	186	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	486	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20155
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	32	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	92	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10131	1	23	1	1	20073	160000	100	20154	20077	20077	20077	20078
160204	20076	151	64	28	80119	100	80019	100	80031	500	640220	0	20056	20076	20076	0	10	10	80131	200	80031	200	160062	20076	20077	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10130	1	23	1	1	20073	160000	100	20166	20077	20077	20077	20077
160204	20077	151	64	29	80119	100	80019	100	80031	500	640220	1	20056	20077	20076	0	9	10	80131	200	80031	200	160062	20076	20077	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10131	1	23	1	1	20073	160000	100	20078	20077	20077	20077	20077
160204	20076	151	127	29	80119	100	80019	100	80031	500	640220	1	20056	20076	20076	0	9	10	80131	200	80031	200	160062	20077	20076	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10131	1	23	1	1	20073	160000	100	20077	20077	20077	20077	20077

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20068	150	0	0	0	0	0	0	353	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	20045	20049	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	2	0	0	10039	8	1	1	20	20	2	1	1	18	18	20270	15	0	160000	10	20046	20046	20046	20050	20048
160024	20045	150	0	0	0	0	0	0	71	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	8	3	2	17	22	2	2	1	19	18	20195	16	0	160000	10	20046	20046	20046	20048	20046
160024	20047	150	0	0	0	0	0	0	216	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20047	20047	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	8	3	1	17	20	1	1	1	18	21	20229	16	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	8	5	1	19	22	2	1	1	18	19	20178	15	0	160000	10	20048	20046	20046	20046	20048
160024	20045	150	0	0	0	0	0	1	44	25	80010	10	80000	10	80000	50	640000	0	1	5	20028	20047	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10041	8	5	1	19	20	1	1	1	18	14	20174	15	0	160000	10	20046	20046	20046	20046	20048
160024	20049	150	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10042	8	5	1	21	20	2	1	1	17	12	20190	16	0	160000	10	20046	20046	20046	20052	20046
160024	20047	151	0	0	0	0	0	0	239	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	1	2	0	10064	8	5	1	17	20	2	1	1	14	18	20345	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	0	44	25	80010	10	80000	10	80296	50	640800	1	1	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20047	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	11	5	1	19	20	2	1	1	19	17	20197	16	0	160000	10	20046	20046	20048	20116	20046
160024	20047	150	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10042	8	3	1	18	20	1	1	1	20	13	20188	15	0	160000	10	20046	20046	20048	20048	20046
160024	20045	150	0	0	0	0	0	0	325	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	3	1	15	20	2	1	1	19	19	20204	15	0	160000	10	20046	20046	20046	20048	20048

Test 5: throughput

Count: 16

Code:

  sri v0.16b, v16.16b, #3
  sri v1.16b, v16.16b, #3
  sri v2.16b, v16.16b, #3
  sri v3.16b, v16.16b, #3
  sri v4.16b, v16.16b, #3
  sri v5.16b, v16.16b, #3
  sri v6.16b, v16.16b, #3
  sri v7.16b, v16.16b, #3
  sri v8.16b, v16.16b, #3
  sri v9.16b, v16.16b, #3
  sri v10.16b, v16.16b, #3
  sri v11.16b, v16.16b, #3
  sri v12.16b, v16.16b, #3
  sri v13.16b, v16.16b, #3
  sri v14.16b, v16.16b, #3
  sri v15.16b, v16.16b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	219	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	71	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	0	0	738	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	2	2	12	16	2	25	1	11	6	40035	30	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	4	2	4	16	4	23	2	5	5	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	42	10022	8	4	1	3	16	4	24	1	5	3	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	0	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	4	1	5	16	2	26	1	9	5	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	11	4	1	5	16	4	24	1	4	9	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	710	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	5	1	5	16	4	21	2	4	6	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	2730	25	160010	10	160000	10	160000	50	1280000	0	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	5	1	3	16	2	22	2	9	10	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	4	1	6	16	4	28	1	3	12	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	3	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	11	5	1	5	16	2	26	2	5	6	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	8	4	1	8	16	2	25	2	3	5	40035	30	5	160000	10	40039	40039	40039	40039	40039

SRI (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations