Firestorm: SRI (vector, 2D) measurements

Code:

  sri v0.2d, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1855	1000	2038	2038	2038	2038	2038
1004	2037	17	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2084	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri v0.2d, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	0	0	0	0	124	19687	44	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18425	7	18745	10581	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	0	0	710	2	16	1	1	19823	0	10000	100	20038	20038	20038	20134	20038
10204	20037	156	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18854	11362	200	10495	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	2	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	8	18745	10100	200	10164	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20085	20037	18422	3	18745	10100	200	10000	200	20000	20037	20131	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	148	19687	25	10100	100	10023	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	2055	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2848963	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	11	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	733	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	0	0	103	19687	25	10010	10	10000	11	10000	50	2847680	0	20054	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20085
10024	20037	155	0	0	0	0	0	9	264	124	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	61	19687	25	10025	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	1	0	0	0	0	201	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	11	10456	65	2851529	1	20018	20037	20037	18444	7	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	2	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	0	3717	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	1	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	3	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	149	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	0	174	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	2	24	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	103	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	2	24	2	2	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	1	139	19686	25	10100	106	10012	100	10000	500	2847521	20018	20037	20085	18428	7	18740	10100	200	10008	200	20016	20086	20085	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	12	0	0	61	19686	25	10145	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	8	16	2	2	19856	0	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20132	20037	18443	3	18767	10010	20	10000	20	20000	20037	20179	1	1	10021	10	9	10	10	10000	10	0	0	3	640	0	2	16	2	2	19852	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	124	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18804	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	24	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	1	2488	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	208	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	3	0	0	187	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10163	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	640	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.2d, v8.2d, #3
  movi v1.16b, 0
  sri v1.2d, v8.2d, #3
  movi v2.16b, 0
  sri v2.2d, v8.2d, #3
  movi v3.16b, 0
  sri v3.2d, v8.2d, #3
  movi v4.16b, 0
  sri v4.2d, v8.2d, #3
  movi v5.16b, 0
  sri v5.2d, v8.2d, #3
  movi v6.16b, 0
  sri v6.2d, v8.2d, #3
  movi v7.16b, 0
  sri v7.2d, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	3	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	4	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10120	3	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	29	25	80116	100	80016	100	80132	500	640988	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	4	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	5	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	3	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	5	16	2	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	4	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10121	4	16	2	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20064	150	24	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20056	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	3	2	1	22	29	2	1	2	5	5	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20056	150	0	149	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20056	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10031	3	1	1	19	28	2	1	1	4	4	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20056	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	13	32	2	1	1	4	3	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	151	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	34	28	2	1	1	3	4	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	151	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	35	28	2	1	1	5	4	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10029	3	2	2	28	28	4	1	1	4	4	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	3	1	1	22	28	2	1	1	4	3	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	0	0	0	0	10026	3	1	1	18	28	2	1	1	3	4	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	21	28	2	1	1	3	3	20049	15	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20033	20052	20052	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10027	3	1	1	20	28	2	1	1	3	4	20049	15	160000	10	20053	20053	20053	20053	20053

Test 5: throughput

Count: 16

Code:

  sri v0.2d, v16.2d, #3
  sri v1.2d, v16.2d, #3
  sri v2.2d, v16.2d, #3
  sri v3.2d, v16.2d, #3
  sri v4.2d, v16.2d, #3
  sri v5.2d, v16.2d, #3
  sri v6.2d, v16.2d, #3
  sri v7.2d, v16.2d, #3
  sri v8.2d, v16.2d, #3
  sri v9.2d, v16.2d, #3
  sri v10.2d, v16.2d, #3
  sri v11.2d, v16.2d, #3
  sri v12.2d, v16.2d, #3
  sri v13.2d, v16.2d, #3
  sri v14.2d, v16.2d, #3
  sri v15.2d, v16.2d, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	310	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	4	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40089	40091
160204	40038	299	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	507	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	2	16	1	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	219	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	0	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	50	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	0	0	0	336	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10022	3	1	1	50	16	2	1	1	20	20	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40096	301	0	0	0	1	0	104	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	7	2	2	1410	10022	3	1	1	42	16	2	1	1	21	21	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	68	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	46	16	2	1	1	21	19	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	39	16	2	1	1	22	16	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	12	0	51	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10058	3	1	1	43	16	2	1	1	23	20	40035	15	5	160000	10	40039	40039	40039	40140	40039
160024	40038	300	0	0	1	1	9	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	33	16	2	1	1	24	22	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	39	16	2	1	1	23	22	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	752	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	1	50	16	4	1	1	14	21	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10022	3	1	19	22	16	2	1	1	22	22	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	534	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	18	59	2	1	1	19	21	40035	15	5	160000	10	40039	40039	40039	40039	40039

SRI (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations