Firestorm: SRI (vector, 2S) measurements

Code:

  sri v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	82	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	63	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	128	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	2	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	147	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	103	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	3	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20054	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10252	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	84	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10172	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10076	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	631	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19931	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	1	16	1	1	19805	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	367	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	1	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	1	16	1	1	19804	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20326	20037	20131	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20132	18443	11	18767	10010	20	10000	20	20000	20037	20037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	103	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	2500	19629	121	10086	10	10072	12	10760	61	2853841	0	20234	20314	20272	18456	29	18859	10924	22	10973	24	21686	20085	20322	7	1	10021	10	9	10	10	10000	10	2	2	0	0	0	11728	4	746	4	64	2	3	20002	0	10000	10	20276	20309	20317	20322	20325
10024	20227	152	0	1	1	6	7	795	528	1	3057	19620	140	10100	10	10060	10	10832	50	2855092	1	20234	20215	20319	18460	27	18883	10468	24	11016	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	0	704	3	16	3	4	19966	0	10000	10	20275	20262	20275	20278	20134
10024	20321	151	0	1	0	5	5	660	440	0	2489	19631	143	10084	13	10072	14	10912	50	2855105	0	20090	20319	20274	18464	14	18878	10826	24	11004	20	20676	20325	20321	6	1	10021	10	9	10	10	10000	10	0	0	0	1	0	10176	4	768	3	64	3	3	20003	1	10000	10	20321	20273	20328	20275	20311
10024	20322	152	0	0	1	6	6	678	528	1	3538	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	11948	0	682	2	16	2	2	19894	0	10000	10	20038	20038	20276	20274	20320
10024	20309	152	1	0	0	7	6	801	528	0	3435	19620	183	10096	12	10036	14	10912	72	2856369	1	20234	20372	20369	18469	28	18927	11076	20	11172	24	22344	20369	20359	8	1	10021	10	9	10	10	10000	10	0	0	2	0	1	6	0	640	2	32	3	2	20042	0	10000	10	20418	20409	20369	20322	20371
10024	20133	150	0	0	1	3	2	414	352	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	12	18804	11228	22	11351	20	21002	20416	20368	8	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	2	688	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.2s, v8.2s, #3
  movi v1.16b, 0
  sri v1.2s, v8.2s, #3
  movi v2.16b, 0
  sri v2.2s, v8.2s, #3
  movi v3.16b, 0
  sri v3.2s, v8.2s, #3
  movi v4.16b, 0
  sri v4.2s, v8.2s, #3
  movi v5.16b, 0
  sri v5.2s, v8.2s, #3
  movi v6.16b, 0
  sri v6.2s, v8.2s, #3
  movi v7.16b, 0
  sri v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	0	0	0	0	0	0	0	71	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	911	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20305	20066
160204	20065	150	0	0	0	0	0	0	1	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	1	1	1	10119	0	84	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	31	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	1	1	1	10119	0	16	0	0	20062	0	160000	100	20156	20066	20066	20066	20147
160204	20065	150	0	0	0	1	132	0	0	29	28	80119	100	80019	100	80031	500	640220	1	20056	20076	20076	9	10	80131	200	80031	200	160062	20076	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10131	1	23	1	1	20074	0	160000	100	20077	20077	20077	20078	20077
160204	20076	151	0	0	0	0	0	0	0	64	28	80119	100	80019	100	80031	500	640220	1	20056	20077	20076	9	10	80131	200	80031	200	160062	20076	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10131	1	23	1	1	20073	0	160000	100	20077	20077	20078	20077	20077
160204	20077	150	0	0	0	0	0	0	0	64	28	80119	100	80019	100	80031	500	640220	0	20056	20077	20077	9	10	80131	200	80031	200	160062	20076	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10130	1	23	1	1	20074	0	160000	100	20077	20077	20078	20078	20078

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20102	150	0	3	44	27	80010	10	80000	10	80000	50	640000	1	0	5	20031	20050	20050	3	21	80211	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	3	3	2	20	25	2	1	1	11	21	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	2	10044	8	1	1	8	25	2	1	1	20	10	20047	40	2	160000	10	20051	20060	20060	20060	20060
160024	20050	150	0	0	44	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10044	8	4	1	20	25	2	1	1	11	21	20047	20	1	160000	10	20060	20060	20060	20051	20051
160024	20050	150	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	5	20031	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10044	3	4	1	20	25	2	1	1	11	21	20047	20	2	160000	10	20060	20060	20060	20051	20051
160024	20050	151	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20040	20050	20050	3	21	80010	20	80000	20	160000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10044	8	4	2	20	25	2	1	1	21	20	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	12	44	29	80010	10	80000	10	80000	50	640000	0	1	5	20031	20050	20050	17	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10044	8	2	1	20	25	2	2	1	10	20	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	8	4	1	8	25	2	1	1	20	10	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20057	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	4	6	0	10044	8	4	1	20	25	2	1	1	21	20	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	1	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20040	20059	20059	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10044	8	4	1	20	25	2	1	1	10	20	20047	40	2	160000	10	20051	20051	20051	20051	20051
160024	20059	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	0	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10044	3	1	1	20	25	2	1	1	20	20	20047	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  sri v0.2s, v16.2s, #3
  sri v1.2s, v16.2s, #3
  sri v2.2s, v16.2s, #3
  sri v3.2s, v16.2s, #3
  sri v4.2s, v16.2s, #3
  sri v5.2s, v16.2s, #3
  sri v6.2s, v16.2s, #3
  sri v7.2s, v16.2s, #3
  sri v8.2s, v16.2s, #3
  sri v9.2s, v16.2s, #3
  sri v10.2s, v16.2s, #3
  sri v11.2s, v16.2s, #3
  sri v12.2s, v16.2s, #3
  sri v13.2s, v16.2s, #3
  sri v14.2s, v16.2s, #3
  sri v15.2s, v16.2s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40057	321	0	0	0	0	3	0	0	0	0	78	25	160112	100	160204	100	160028	500	1280196	0	40028	40048	40048	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	322	0	0	0	0	0	0	0	0	0	233	25	160108	100	160008	100	160020	500	1280132	1	40028	40048	40048	19976	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	0	0	0	303	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320262	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10168	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40167	40089	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	470	0	1	1	1	10118	0	16	1	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	1	0	2	0	0	0	124	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160129	200	320264	40111	40110	3	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40162	40039	40039	40039	40048
160204	40048	322	0	1	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	311	0	0	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	57	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	0	0	1	0	0	0	64	26	160116	100	160016	100	160028	500	1281724	0	40028	40048	40049	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	2	0	0	0	0	2	2	2	10129	1	23	1	1	40045	0	160000	100	40049	40050	40049	40049	40049
160204	40171	311	0	0	1	0	0	0	0	0	0	64	26	160116	100	160016	100	160225	500	1280196	0	40028	40049	40048	19976	10	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	0	2	2	2	10128	1	23	1	1	40045	0	160000	100	40050	40049	40049	40050	40049
160204	40049	311	0	0	0	0	0	0	0	0	0	64	27	160116	100	160016	100	160028	500	1280196	0	40088	40048	40049	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	2	2	0	0	0	0	2	2	2	10129	1	23	1	1	40045	0	160000	100	40215	40049	40049	40049	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	299	0	0	0	0	809	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	5	5	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	3	5	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	3	0	10022	3	1	1	4	16	2	1	1	4	4	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	6	1	1	4	16	2	1	1	4	4	40035	15	5	160000	10	40100	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	7	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	4	5	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	74	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	5	5	40035	30	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	2	10022	3	1	1	4	16	2	1	1	4	3	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	2	0	0	10022	3	1	1	3	16	4	1	1	4	4	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	40019	0	40038	40038	19995	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	4	4	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	2	3	16	2	1	2	4	3	40035	15	5	160000	10	40039	40039	40039	40039	40039

SRI (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations