Firestorm: SRI (vector, 4S) measurements

Code:

  sri v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	141	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	84	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	100	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	105	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	117	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	156	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18429	12	18740	10261	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	1	1	1	717	0	16	0	0	19801	22	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18429	7	18741	10100	200	10008	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	0	0	0	710	1	16	2	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	44	10100	100	10000	100	10000	500	2848963	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	19877	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	7030	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10048	100	10000	500	2848650	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	6	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20086	20038	20038
10204	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20133	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	6	0	0	0	0	710	1	16	1	1	19861	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	441	19687	25	10169	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	24	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	1	1564	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	3	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20085
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2848963	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	0	0	0	710	1	16	1	1	19827	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10100	100	10012	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20182	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	0	0	0	0	710	1	16	1	1	19825	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	156	0	0	0	0	0	0	61	19687	25	10010	10	10000	12	10000	50	2847680	0	20054	20132	20037	18459	3	18767	10010	20	10830	20	20338	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	45	4	1	640	2	16	2	2	19785	2	10000	10	20038	20038	20038	20038	20038
10024	20085	160	0	0	0	0	6	0	441	19676	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	9	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	366	19687	25	10034	10	10000	10	10000	50	2848963	0	20018	20037	20037	18444	3	18767	10010	20	10492	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	78	2	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20085	20037	1	1	10021	10	9	10	10	10000	10	0	0	4	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	61	19687	25	10010	11	10048	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	2	0	640	3	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	1	0	0	117	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20084	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20084	20276	20132	20038
10024	20037	155	0	0	0	0	0	0	166	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18448	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	128	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10162	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	61	19654	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri v0.4s, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	161	0	1	0	0	0	0	0	0	885	19675	0	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	5	0	2000	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	1	0	0	0	0	82	19686	0	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10256	200	10008	200	20016	20085	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	4	1	1	1	861	0	74	2	2	20052	10	10000	100	20323	20323	20373	20375	20134
10204	20323	158	0	0	1	6	7	546	616	0	5061	19618	0	143	10189	117	10036	119	10912	636	2855105	0	20126	20371	20376	18436	42	18865	11185	224	11144	224	22334	20324	20369	8	1	10201	100	99	100	100	10000	100	0	2	2	0	0	0	16050	0	1	1	1	717	0	16	0	0	19800	1	10000	100	20181	20182	20277	20133	20183
10204	20181	156	1	0	1	4	4	414	440	1	2243	19631	0	125	10144	108	10024	106	10152	549	2848785	0	20162	20086	20132	18449	30	18813	10872	216	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	2	4	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20227	20038
10204	20084	155	1	0	1	0	0	9	352	1	4074	19609	0	162	10216	122	10084	122	10456	642	2856169	0	20270	20414	20459	18434	40	18873	11344	220	11171	228	22348	20371	20326	8	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	7990	2	1	1	1	873	0	81	1	0	20148	10	10000	100	20374	20370	20363	20133	20421
10204	20227	158	1	0	1	8	8	924	88	1	162	19686	0	25	10100	100	10000	100	10000	500	2847521	0	20270	20181	20085	18446	31	18796	11185	218	11009	212	22690	20180	20181	8	1	10201	100	99	100	100	10000	100	2	0	0	0	1	4	7810	2	1	1	1	792	0	40	0	1	19945	8	10000	100	20325	20409	20372	20313	20218
10204	20180	156	1	0	0	7	2	9	528	0	2097	19686	0	84	10100	104	10084	100	11216	544	2853802	0	20126	20181	20037	18439	7	18741	10564	200	10008	200	22344	20418	20410	8	1	10201	100	99	100	100	10000	100	2	0	2	0	1	4	16015	0	1	1	1	717	0	16	2	0	20146	9	10000	100	20277	20275	20230	20375	20278
10204	20132	163	0	1	1	6	4	528	0	0	61	19686	0	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	2	7925	0	1	1	1	921	0	95	0	3	20022	9	10000	100	20421	20409	20314	20095	20038
10204	20037	156	0	0	0	1	0	0	0	1	377	19686	13	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20134	20038	20038
10204	20037	155	0	0	0	0	0	0	0	1	97	19686	0	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20087	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bc	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	156	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	176	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	0	640	0	0	2	16	2	2	19825	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	0	20018	0	20084	20037	18443	3	18767	10391	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20086	20132	20038	20085	20038
10024	20037	155	0	0	0	0	0	0	0	0	628	19686	25	10010	10	10000	10	10000	50	2847521	0	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	29	0	0	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	3	0	3	0	0	640	0	0	3	49	2	2	19931	0	10000	10	20180	20131	20230	20275	20179
10024	20404	163	0	0	1	4	1	18	172	0	61	19686	25	10010	10	10012	10	10000	50	2847521	0	0	20018	3	20037	20037	18447	8	18767	10010	20	10000	20	20326	20037	20037	1	1	10021	10	9	10	10	10000	10	0	6	0	2	0	3	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	3	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2060	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	88	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	0	0	2	16	2	2	19786	1	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	44	10010	12	10000	10	10000	50	2847521	1	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	0	0	640	0	0	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	0	20054	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	4	0	2080	0	0	640	0	0	2	16	2	4	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.4s, v8.4s, #3
  movi v1.16b, 0
  sri v1.4s, v8.4s, #3
  movi v2.16b, 0
  sri v2.4s, v8.4s, #3
  movi v3.16b, 0
  sri v3.4s, v8.4s, #3
  movi v4.16b, 0
  sri v4.4s, v8.4s, #3
  movi v5.16b, 0
  sri v5.4s, v8.4s, #3
  movi v6.16b, 0
  sri v6.4s, v8.4s, #3
  movi v7.16b, 0
  sri v7.4s, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	155	0	0	0	0	0	0	0	0	492	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	66	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	88	0	94	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160258	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	2	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20145	20066	20066	20066
160204	20065	155	0	0	0	2	0	0	0	0	93	319	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160464	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20091
160204	20144	161	1	1	0	0	0	0	0	0	471	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	132	0	0	52	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	1	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20223	6	12	80128	200	80131	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	178	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	158	0	0	0	0	0	0	0	0	465	84	80116	100	80217	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	71	25	80116	100	80016	100	80028	500	640196	1	20173	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20128	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	156	0	0	0	0	0	0	0	21	65	27	80010	10	80000	10	80000	50	640000	1	1	5	20034	20050	20050	3	21	80010	20	80000	20	160000	20205	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10032	13	3	1	13	25	2	1	2	3	9	20047	20	1	160000	10	20051	20051	20051	20051	20060
160024	20051	161	0	0	0	0	0	0	0	15	44	27	80010	10	80000	10	80199	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1	0	0	0	10029	13	6	1	9	25	2	1	1	5	5	20047	40	2	160000	10	20060	20060	20060	20051	20051
160024	20050	155	0	0	0	0	0	408	0	17	882	27	80010	10	80000	10	80000	50	640000	0	1	10	20031	20050	20050	3	21	80010	20	80000	20	160202	20129	20151	2	1	160021	10	9	10	10	160000	10	0	6	0	0	0	0	0	0	10028	13	7	1	9	25	2	2	1	9	5	20047	20	1	160000	10	20051	20051	20051	20051	20052
160024	20050	155	0	0	0	0	0	0	0	17	153	29	80010	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80206	20	80000	20	160000	20150	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	13	6	1	5	25	4	1	1	3	9	20047	20	2	160000	10	20051	20051	20060	20126	20051
160024	20059	155	0	0	0	0	0	0	0	13	44	76	80108	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10032	13	6	1	9	25	4	1	1	12	5	20056	40	1	160000	10	20051	20051	20051	20051	20051
160024	20050	155	0	0	0	0	0	0	0	16	174	27	80010	10	80000	10	80000	50	640000	0	1	10	20031	20143	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	13	7	1	5	25	2	1	1	9	5	20047	40	1	160000	10	20051	20060	20130	20051	20051
160024	20050	156	0	0	0	0	0	0	0	16	92	27	80010	10	80100	10	80000	50	640000	1	1	10	20031	20052	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10028	13	6	1	5	26	2	1	1	3	5	20177	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	156	0	0	0	0	0	0	0	15	67	27	80010	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	13	6	1	3	25	2	1	1	5	5	20047	20	1	160000	10	20051	20051	20060	20051	20060
160024	20050	155	0	0	0	0	3	0	0	0	109	27	80010	10	80000	10	80000	50	640000	1	1	0	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	3	1	1	3	25	2	1	1	4	9	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20129	155	1	0	0	0	0	0	0	0	44	27	80010	10	80000	10	80000	50	640000	0	1	0	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10031	6	1	2	11	25	2	1	1	3	5	20111	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  sri v0.4s, v16.4s, #3
  sri v1.4s, v16.4s, #3
  sri v2.4s, v16.4s, #3
  sri v3.4s, v16.4s, #3
  sri v4.4s, v16.4s, #3
  sri v5.4s, v16.4s, #3
  sri v6.4s, v16.4s, #3
  sri v7.4s, v16.4s, #3
  sri v8.4s, v16.4s, #3
  sri v9.4s, v16.4s, #3
  sri v10.4s, v16.4s, #3
  sri v11.4s, v16.4s, #3
  sri v12.4s, v16.4s, #3
  sri v13.4s, v16.4s, #3
  sri v14.4s, v16.4s, #3
  sri v15.4s, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40038	310	0	0	0	1	0	88	0	29	25	160108	100	160008	100	160020	500	1286280	0	40019	0	40038	40038	19977	0	6	19986	160120	200	160032	200	320064	40038	40038	3	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	2	16	3	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	2	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	2	16	2	2	40035	0	160000	100	40039	40166	40039	40039	40039
160204	40038	310	1	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40094	19977	0	11	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	2	1	1	1	10118	0	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40111
160204	40038	310	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	0	6	19989	160120	200	160032	200	320256	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	2	16	2	2	40035	0	160000	100	40039	40039	40039	40148	40039
160204	40038	310	0	0	0	0	0	0	0	29	25	160108	100	160104	100	160020	500	1280132	0	40019	0	40143	40089	19977	0	6	19989	160224	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	3	16	2	1	40035	0	160000	100	40039	40039	40039	40039	40156
160204	40038	310	0	0	0	0	0	0	0	309	25	160108	100	160008	100	160020	500	1280132	0	40093	0	40096	40038	19977	0	15	20040	160120	200	160032	200	320064	40108	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	2	0	0	1	1	1	10118	0	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	0	16	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	2	125	2	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	322	0	0	0	0	0	0	0	205	25	160297	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	0	0	1	1	1	10118	0	2	38	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	0	0	0	0	0	0	0	1421	128	160108	100	160008	100	160020	500	1281676	0	40019	0	40038	40038	19977	0	6	19989	160120	200	160032	200	320654	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10118	0	2	16	2	4	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	310	1	0	0	0	0	0	0	6394	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10152	0	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40120	311	0	1	1	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	0	40019	40087	40038	19996	3	20018	160108	20	160098	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10041	3	3	1	7	16	2	1	1	3	6	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	311	0	0	0	0	0	0	0	0	45	25	160010	10	160095	10	160000	50	1281544	0	1	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	2	0	0	0	0	3	0	0	10024	8	1	2	4	16	2	2	2	3	4	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	310	0	0	0	1	2	426	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	3	1	6	16	4	1	1	2	3	40209	30	10	160000	10	40039	40268	40039	40039	40039
160024	40038	310	0	0	0	0	0	3	0	0	51	96	160010	10	160000	10	160097	50	1280000	1	1	5	40097	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	2	1	4	104	2	1	1	2	4	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	311	0	0	0	0	0	0	0	0	150	25	160010	10	160279	10	160098	50	1280000	1	0	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40108	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	4	0	10022	11	3	1	3	16	2	1	1	2	2	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	311	0	0	0	0	1	192	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40038	19996	3	20018	160107	20	160485	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	11	2	1	6	16	4	1	1	3	5	40035	30	10	160000	10	40039	40039	40039	40039	40161
160024	40087	310	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160099	50	1280000	0	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	0	0	0	10022	8	2	1	6	16	2	1	1	3	5	40035	30	5	160000	10	40039	40039	40039	40039	40088
160024	40090	310	0	0	0	0	0	0	0	0	45	43	160197	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	4	0	0	0	10024	8	2	1	4	16	2	1	1	2	4	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	310	0	0	0	0	1	189	0	0	45	67	160383	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40138	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	2	1	5	16	2	1	2	3	4	40035	30	10	160000	10	40039	40039	40039	40039	40039
160024	40038	311	0	0	0	0	4	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20046	160106	20	160098	20	320192	40038	40038	3	1	160021	10	9	10	10	160000	10	0	0	0	0	0	1533	0	0	10022	8	2	1	4	16	2	1	1	4	4	40035	15	5	160000	10	40039	40090	40039	40039	40039

SRI (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations