Firestorm: SRI (vector, 8H) measurements

Code:

  sri v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	15	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	1	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	17	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	17	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	17	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	17	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	21	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	159	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	2479	19632	120	10180	125	10060	131	10760	659	2853981	0	20198	20037	20277	18440	0	29	18835	10896	200	10830	216	21318	20275	20228	6	1	10201	100	99	100	100	10000	100	0	2	7	0	9845	802	1	33	1	1	19970	29	10000	100	20275	20230	20267	20229	20275
10204	20085	152	1	0	6	6	816	440	2982	19676	160	10220	134	10072	139	10760	706	2854095	0	20198	20321	20321	18444	0	33	18907	10898	222	10332	220	21658	20321	20321	6	1	10201	100	99	100	100	10000	100	2	0	0	0	0	710	1	25	1	1	19827	0	10000	100	20278	20181	20183	20372	20086
10204	20122	151	0	1	3	3	270	146	1060	19654	80	10154	116	10036	124	10420	665	2851529	1	20090	20134	20229	18432	0	17	18798	10573	215	10168	210	20000	20273	20180	3	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	37	1	1	19791	0	10000	100	20038	20038	20038	20374	20038
10204	20037	161	1	0	3	4	399	440	2225	19687	25	10100	100	10000	100	10000	500	2847680	0	20054	20084	20133	18429	0	9	18761	10424	202	10326	206	20660	20133	20134	2	1	10201	100	99	100	100	10000	100	2	2	0	2	4023	710	1	25	2	1	19791	29	10000	100	20038	20038	20038	20038	20227
10204	20186	157	1	1	0	0	0	0	160	19687	45	10100	100	10000	100	10000	626	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	489	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18456	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	9	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri v0.8h, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	84	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10012	103	10152	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	2	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	82	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	126	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	206	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	118	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	229	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20084	20084	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	220	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10180	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	105	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	0	0	0	0	0	0	145	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	145	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	669	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	213	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	957	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	6	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.8h, v8.8h, #3
  movi v1.16b, 0
  sri v1.8h, v8.8h, #3
  movi v2.16b, 0
  sri v2.8h, v8.8h, #3
  movi v3.16b, 0
  sri v3.8h, v8.8h, #3
  movi v4.16b, 0
  sri v4.8h, v8.8h, #3
  movi v5.16b, 0
  sri v5.8h, v8.8h, #3
  movi v6.16b, 0
  sri v6.8h, v8.8h, #3
  movi v7.16b, 0
  sri v7.8h, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20080	150	0	0	0	0	0	0	71	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20130	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	29	25	80116	100	80016	100	80131	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	1	1	10131	1	23	1	1	20074	0	160000	100	20078	20077	20077	20078	20077
160204	20131	150	0	0	0	0	0	0	64	28	80119	100	80019	100	80031	500	640220	0	20056	20076	20076	9	10	80131	200	80031	200	160062	20076	20076	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	2	2	2	10146	1	23	1	1	20073	0	160000	100	20078	20078	20078	20077	20078
160204	20077	150	0	0	0	0	0	0	64	28	80119	100	80019	100	80031	500	640220	0	20056	20076	20076	9	10	80131	200	80031	200	160062	20077	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	2	2	2	10130	1	23	1	1	20074	0	160000	100	20078	20077	20077	20078	20077
160204	20076	150	0	0	0	0	0	0	64	28	80119	100	80019	100	80031	500	640220	1	20056	20076	20077	9	10	80131	200	80031	200	160062	20076	20076	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	2	2	2	10130	1	23	1	1	20074	0	160000	100	20078	20077	20077	20078	20077
160204	20076	150	0	0	0	0	0	0	127	28	80119	100	80019	100	80031	500	640220	0	20056	20076	20077	10	10	80131	200	80031	200	160062	20076	20076	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	2	2	2	10130	1	23	1	1	20074	0	160000	100	20078	20078	20078	20078	20077
160204	20077	150	0	0	0	0	0	0	127	28	80119	100	80019	100	80031	500	640220	0	20056	20076	20077	9	10	80131	200	80031	200	160062	20077	20076	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	2	2	2	10131	1	23	1	1	20073	0	160000	100	20077	20077	20077	20078	20077

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20106	150	0	0	0	0	0	3	107	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	46	9	10046	3	1	1	25	34	4	2	2	24	23	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	3	45	27	80010	10	80000	10	80000	50	640000	1	1	20040	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	3	0	10048	3	1	2	23	25	2	1	1	23	23	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	1	478	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	3	1	1	23	25	2	1	1	22	25	20047	20	1	160000	10	20051	20051	20060	20051	20051
160024	20050	150	0	0	0	0	0	2	44	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80111	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	1	0	10047	3	1	1	25	25	2	1	1	27	24	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	1	44	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10050	3	1	1	24	25	2	1	1	24	24	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	1	364	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10046	3	1	1	23	25	2	1	1	22	23	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	1	109	27	80010	10	80077	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10047	3	1	1	24	34	4	1	2	24	24	20056	40	2	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	36	0	1	109	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	3	10047	3	1	1	24	25	2	1	1	25	24	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	2	132	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	6	1	2	23	25	2	1	1	23	23	20056	20	1	160000	10	20060	20051	20060	20051	20051
160024	20050	150	0	0	0	0	0	2	44	27	80010	10	80000	10	80000	50	640000	2	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10047	3	1	1	24	34	2	2	1	27	25	20056	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  sri v0.8h, v16.8h, #3
  sri v1.8h, v16.8h, #3
  sri v2.8h, v16.8h, #3
  sri v3.8h, v16.8h, #3
  sri v4.8h, v16.8h, #3
  sri v5.8h, v16.8h, #3
  sri v6.8h, v16.8h, #3
  sri v7.8h, v16.8h, #3
  sri v8.8h, v16.8h, #3
  sri v9.8h, v16.8h, #3
  sri v10.8h, v16.8h, #3
  sri v11.8h, v16.8h, #3
  sri v12.8h, v16.8h, #3
  sri v13.8h, v16.8h, #3
  sri v14.8h, v16.8h, #3
  sri v15.8h, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40057	300	0	0	0	0	0	0	0	113	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	0	250	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40076	40039
160204	40038	299	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320272	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	3	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40090
160204	40038	300	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	16	0	0	0	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40046	299	0	0	0	99	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	28	16	2	1	1	24	22	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	2	21	16	2	1	2	21	24	40035	0	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	22	16	2	1	1	26	24	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	171	25	160010	10	160000	10	160000	50	1280000	0	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	22	16	2	1	1	22	22	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	23	16	2	1	1	22	21	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40098	40038	40139	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	15	16	2	1	1	21	21	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	5535	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	22	16	2	1	1	23	19	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	1	182	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	1	0	10022	3	1	1	21	16	2	1	1	23	21	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	129	25	160010	10	160000	10	160108	50	1280000	1	1	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	6	1	1	23	16	2	1	1	25	20	40035	0	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	45	50	160103	10	160095	10	160098	50	1280776	1	1	40112	40156	40155	20013	7	20047	160109	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	24	16	2	1	1	24	24	40035	0	20	8	160000	10	40039	40039	40039	40039	40039

SRI (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations