Firestorm: SRI (vector, D) measurements

Code:

  sri d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	89	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sri d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	54	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	63	0	61	19687	25	10100	100	10000	100	10000	577	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	0	2838	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	21	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	144	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	351	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	24	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	36	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	96	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sri d0, d0, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	632	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	4	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	762	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	96	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	135	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	1	560	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	1	1	1	722	2	24	2	2	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	251	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	66	292	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	168	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	210	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri d0, d8, #3
  movi v1.16b, 0
  sri d1, d8, #3
  movi v2.16b, 0
  sri d2, d8, #3
  movi v3.16b, 0
  sri d3, d8, #3
  movi v4.16b, 0
  sri d4, d8, #3
  movi v5.16b, 0
  sri d5, d8, #3
  movi v6.16b, 0
  sri d6, d8, #3
  movi v7.16b, 0
  sri d7, d8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	153	1	1	0	1063	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	1	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	0	720	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	174	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	1	1	0	190	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20130	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	0	159	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	1	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	0	94	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	1	1	0	117	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	0	52	25	80116	100	80016	100	80028	500	640196	0	1	20044	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20076	150	3	0	0	0	0	157	27	80010	10	80000	10	80000	50	640000	1	1	0	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10046	11	2	1	24	34	4	2	2	18	19	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	1	1	0	0	1	419	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	20059	20059	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1933	10048	11	3	1	15	34	4	1	2	16	21	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	2	0	0	0	0	610	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10040	3	1	1	19	25	4	2	2	20	19	20056	20	1	160000	10	20170	20051	20060	20060	20051
160024	20059	156	1	2	0	0	0	564	29	80010	10	80000	10	80000	50	640000	0	1	0	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10044	16	7	2	14	34	4	2	2	13	18	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	1	1	0	0	0	50	29	80010	10	80000	10	80000	50	640000	0	0	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10046	6	2	2	18	34	4	2	2	18	18	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	151	0	0	0	0	0	398	27	80010	10	80000	10	80000	50	640000	0	1	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10043	6	2	2	17	34	4	2	2	20	20	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	151	1	1	0	0	0	119	29	80010	10	80000	10	80000	50	640000	0	0	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	3	0	0	10048	6	7	2	17	34	4	2	2	19	17	20056	40	2	160000	10	20060	20051	20060	20060	20060
160024	20059	150	1	1	0	0	0	689	29	80010	10	80000	10	80000	50	640000	0	0	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10043	6	7	2	18	34	4	2	2	18	20	20056	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	1	2	0	0	1	56	29	80010	10	80000	10	80000	50	640000	0	0	0	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	10045	6	7	2	21	34	4	2	2	21	18	20056	20	1	160000	10	20060	20060	20060	20060	20060
160024	20059	151	2	1	0	0	0	62	29	80010	10	80000	10	80000	50	640000	0	1	10	20105	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10045	6	6	2	13	34	4	2	2	18	18	20056	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  sri d0, d16, #3
  sri d1, d16, #3
  sri d2, d16, #3
  sri d3, d16, #3
  sri d4, d16, #3
  sri d5, d16, #3
  sri d6, d16, #3
  sri d7, d16, #3
  sri d8, d16, #3
  sri d9, d16, #3
  sri d10, d16, #3
  sri d11, d16, #3
  sri d12, d16, #3
  sri d13, d16, #3
  sri d14, d16, #3
  sri d15, d16, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	21	155	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320272	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40241	40039
160204	40038	299	1	12	71	25	160108	100	160389	100	160020	500	1283284	0	40019	40143	40038	19977	6	20040	160120	200	160425	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	4	9	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160136	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	3	1	19	16	2	1	17	20	20	40035	16	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	1	1	0	0	0	12	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	6	1	21	16	2	1	17	15	14	40035	16	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	5	1	21	16	2	2	16	17	17	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	710	25	160010	10	160000	10	160000	50	1280000	0	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	2	19	16	2	1	15	15	15	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	1	17	16	2	1	16	19	20	40035	16	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	1	16	16	2	1	18	16	14	40035	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	5	1	21	16	2	2	17	18	19	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	16	5	2	19	16	4	1	18	19	19	40035	15	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	2	12	1716	792	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320264	40038	40038	1	1	160021	10	9	10	10	160000	10	4	0	0	0	10095	13	5	2	18	16	4	2	19	14	17	40035	30	10	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	6	1	19	16	2	1	18	16	17	40035	16	5	160000	10	40039	40039	40039	40039	40039

SRI (vector, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations