Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSHL (vector, 4S)

Test 1: uops

Code:

  srshl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037221561254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000373116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037226361254825100010001000398313130183037303724153289510001000200030373037111001100000673116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100030673116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000373116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000001573116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  srshl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000012429548251010010010000100100005004277313153001830037300372826532874510100200100002002000030037300371110201100991001001000010000000007105121642296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313153001830037300372826532874510100200100002002000030037300371110201100991001001000010000010007105121624296340100001003003830038300383003830038
102043003722500400006129548251010010010000100100005004277313153001830037300372826532874510100200100002002000030037300371110201100991001001000010000000007105121622296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313153001830037300852826535288751118521811160219223183037230372711020110099100100100001000201219429284651274322988129100001003032530372303713037330397
102043037122710779331760458129494164101951391005614311192728428681211030270303723018028291312887211182222111482242197430374303738110201100991001001000010042310193204869101272222990228100001003017930375304193037230373
1020430370228018792468214570294946610197152100641481134163742881691103034230471304222829418289091135423010992230229623041830467101102011009910010010000100000000071010221622296340100001003003830038300383003830038
10204300372250000300612954825101001001000010010000500427731311030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071010021622297390100001003003830038300383003830038
10204300372250000000612953925101001001000010010000500427731311030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071010121622296340100001003003830038300383003830227
102043003722400000002102954825101001001000010010000500427731311030018300373003728265328745101002001000020020666300373003711102011009910010010000100000000071010121622296340100001003003830038300383003830038
10204300372240000000612954825101001001000010010000500427731311030018300373003728265328745101002001000020020000300373003711102011009910010010000100000100071010121622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006404162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  srshl v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000011842954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250000010222954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830085
10204300372250000010032954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296344100001003003830038300383003830038
10204300372250000010042954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372240000010682954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000008772954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000156208612953925101251001000810010000500427731330054300853013328265328745101002001000020020000301323008431102011009910010010000100000410571011611296340100001003003830038300383003830087
1020430037225000001032954825101001001000010010000500427731330018300373008528265328745101002001000020021982303233003741102011009910010010000100400071011611296340100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510020101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300852828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225082295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402172229630010000103003830038300383003830038
10024300372250265295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250276295482510010101000012101495042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630210000103003830038300383003830038
10024300372250231295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229774010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  srshl v0.4s, v8.4s, v9.4s
  srshl v1.4s, v8.4s, v9.4s
  srshl v2.4s, v8.4s, v9.4s
  srshl v3.4s, v8.4s, v9.4s
  srshl v4.4s, v8.4s, v9.4s
  srshl v5.4s, v8.4s, v9.4s
  srshl v6.4s, v8.4s, v9.4s
  srshl v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039150000041258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000600511021611200360800001002004020040200402004020040
80204200391500000254258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000062258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000041258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000041258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
8020420039150000083258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000010000511011611200360800001002004020040200402004020040
802042003915000001021258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040
80204200391500000412580100100800001008000050064000002002020039200399973039997801002008000020016000020039200391180201100991001008000010000350300511011611200360800001002004020040200402004020040
80204200391500000127258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000040300511011611200360800001002004020040200402004020040
802042003915000001002258010010080000100800005006400000200202003920039997303999780100200800002001600002003920039118020110099100100800001000000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150010525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020141611112003680000102004020040200402004020040
800242003915007052580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010039965020131612132003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010041125020101611112003680000102004020040200402004020040
800242003915008225800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020111612122003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100401265020121613132003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502011168122003680000102004020040200402004020040
800242003915005662580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502013161282003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100105020131614122003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010030485020131613122003680000102004020040200402004020040
800242003915008225800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020111615152003680000102004020040200402004020040