Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSHL (vector, 8H)

Test 1: uops

Code:

  srshl v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
1004303722000021032548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372310002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372210002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372210902822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372310002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372210002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372310002822548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
1004303723100021982548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
1004303723100021032548251000100010003983133018303730372415328951000100020003037303711100110000077416442630100030383038303830383038

Test 2: Latency 1->2

Code:

  srshl v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313030018300373003728272728740101002001000820020016300373003711102011009910010010000100000011171801600296470100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728272728740101002001000820020016300373003711102011009910010010000100000011171801600296460100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100016000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722509429548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216122963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010001000640216222963010000103003830038300383003830038
1002430037225002852954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250264612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500822954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722514488612954825100101010000101000050427731313001830037300372828772876710010201000020200003003730037111002110910101000010000000640216222977410000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000120640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  srshl v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037224961295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430085225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001015050042773133001830037300372826532874510100200100002002000030037300851110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225061295482510100100100071001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300853003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  srshl v0.8h, v8.8h, v9.8h
  srshl v1.8h, v8.8h, v9.8h
  srshl v2.8h, v8.8h, v9.8h
  srshl v3.8h, v8.8h, v9.8h
  srshl v4.8h, v8.8h, v9.8h
  srshl v5.8h, v8.8h, v9.8h
  srshl v6.8h, v8.8h, v9.8h
  srshl v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915000000540412580100100800001118000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511021611200360800001002004020040200402004020040
802042003914900000360412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000210412580100100800001008000050064000012002020039200399973399978010020080000200160000200392009811802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000240412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000510412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
80204200391500000090412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000600412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000540412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011611200360800001002004020040200402004020040
802042003915000000570412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000000511011612200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200591506640258001010800001080000506400001200202003920039999531001980010208000020160000200392003911800211091010800001000502012161032003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020616642003680000102004020040200402004020040
80024200391505104025800101080000108000050640000120020200392003999923100198001020800002016000020039200391180021109101080000100050207161142003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198012220800002016000020039200391180021109101080000100050207165122003680000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001005805020516652003680000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001010502010161042003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999953100198001020800002016000020039200391180021109101080000100050206165102003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399995310019800102080000201600002003920039118002110910108000010005020516492003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399995310019800102080000201600002003920039118002110910108000010005020516572003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050205165112003680000102004020040200402004020040