Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSHL (vector, D)

Test 1: uops

Code:

  srshl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037231061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037220061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037230661254825100010001000398313030183037303724153289510001000200030373037111001100000073216222702100030383038303830383038
10043037220061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  srshl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007103162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250082295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372330061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000036061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006632162229630010000103003830038300383003830038
10024300372250000000103295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722400000006129512159100701510056141104382428545513027030322305582831933289101090722101622422280303213036681100211091010100001022212558628082815329846410000103036730369303683037130413
100243036722810077972616467329485186100711710032151089460428681203030630370303692831116288961120620100002220660300373003721100211091010100001000000006402162229854510000103037030274303203008530365
1002430321227100767295283230294841601007813100641211043764285455030270302723051228316372889310458261114022222983036830083811002110910101000010222121952508333404329964410000103041530455304653045330414

Test 3: Latency 1->3

Code:

  srshl d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000214200003013230084111020110099100100100001000003071021622296340100001003003830038300383003830038
10204300372250000124295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037311020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001004000071021622296340100001003003830038300383003830038
102043003722500003849295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071021622296340100001003003830038300383003830038
10204300372250000726295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064031622296300010000103003830038300383003830038
10024300372240006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038
10024300372240006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100066021622296300010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010461264021622296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021722296300010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100064021622296300010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  srshl d0, d8, d9
  srshl d1, d8, d9
  srshl d2, d8, d9
  srshl d3, d8, d9
  srshl d4, d8, d9
  srshl d5, d8, d9
  srshl d6, d8, d9
  srshl d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511021611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
802042003915000000360412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
8020420039150000002790412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
802042003915000000004212580100100800001008000050064000020020020039200399973039997801002008000020016027220039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020070020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000020020020039200399973039997801002008000020016000020039200391180201100991001008000010000000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150012070525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020716532003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020140200392003999963100198001020800002016000020039200391180021109101080000100005020516532003680000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100005020316462003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020616352003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020516352003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020516532003680000102004020040200402004020040
80024200391500904025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020516462003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020416352003680000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100005020416532003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100005020416552003680000102004020040200402004020040