Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSHR (vector, 2D)

Test 1: uops

Code:

  srshr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230061254725100010001000398160130183037303724143289510001000100030373037111001100010373116112629100030383038303830383038
10043037220361254725100010001000398160030183037303724143289510001000100030373037111001100012073116112629100030383038303830383038
100430372300126254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230061253825100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037231061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230061254725100010001000398160130183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
10043037220061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037230061254725100010001000398160130183037303724143289510001000100030373037111001100000673116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  srshr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000441295472510100100100001001000050042771600300180300373003728264328745102502001000020010000300373003711102011009910010010000100107101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300180300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300180300373003728264328745101002001000020010000300373003711102011009910010010000100407101161129633100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001005507101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771600300180300373003728264328745101002001000020010000300373003711102011009910010010000100107101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300180300373003728264328745101002001000020010000300373003711102011009910010010000100397101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771600300180300373003728264328745101002001000020010000300373003711102011009910010010000100067101161129633100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001001007101161129633100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001001007101161129633100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771600300180300373003728264328745101002001000020010000300373003711102011009910010010000100107101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000033006402162229629010000103003830038300383003830038
10024300372250000006129547251001810100001010000504277160003001830037300372828632876710010201000020100003003730037111002110910101000010000000135006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000103006402162229629210000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000103006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000200006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000103006402162229629010000103003830038300383003830038
100243003722400000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000103006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000203006402162229629010000103003830038300383003830038
100243003722400000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000006006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000203006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  srshr v0.2d, v8.2d, #3
  srshr v1.2d, v8.2d, #3
  srshr v2.2d, v8.2d, #3
  srshr v3.2d, v8.2d, #3
  srshr v4.2d, v8.2d, #3
  srshr v5.2d, v8.2d, #3
  srshr v6.2d, v8.2d, #3
  srshr v7.2d, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915000030402580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000010311151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000311151180160020036800001002004020040200402004020040
8020420039151000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000210011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000010011151180160020036800001002004020040200402004020040
802042003915000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100035020116112003680000102004020040200402004020040
800242003915010402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180022109101080000100035020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100235020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100035020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100005020116112003680000102004020040200402004020093
800242003915200402580010108000010800005064000002002020039200399996310019800102080000208000020039200912180021109101080000100065020216112003680000102004020040200402004020040
8002420039150012135258001010800001080000506400000200202003920039999631001980010208010620800002003920039118002110910108000010004865020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100005020116112003680000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001002105020116112003680000102004020040200402004020040