Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

SRSHR (vector, 4S)

Test 1: uops

Code:

  srshr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e1f3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037220061254725100010001000398160130183037303724143289510001000100030373037111001100003073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723008225472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372212015625472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723008225472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  srshr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030818191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250000006129547251010010010000100100005004277160130018300373003728271728740101002001000820010008300373003711102011009910010010000100000011171701600296450100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160130018300373003728271728740101002001000820010008300373003711102011009910010010000100010011171701600296450100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160130018300373003728271728741101002001000820010008300373003711102011009910010010000100000011171801600296450100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160030018300373003728271728741101002001000820010008300373003711102011009910010010000100010000071012511296330100001003003830038300383003830038
1020430037225100120120222952944101121311001613410300642428087413009030132301332826715287801042520410330208103303013130134311020110099100100100001002028532000754133112966625100001003008530086300853008730134
1020430085225011348120074529529441013211610008114101505174277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100013000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
102043003722400012006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100002681200071011612296690100001003003830038300873003830038
10204300372250001440082929538251010010010000127100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011601296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030b181e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc2cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002430037224009906129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225009606129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640335222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010002640216222962910000103003830038300383003830038
1002430037225006606129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250001086129547251001010100001010000504277160030018300373003728286032876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  srshr v0.4s, v8.4s, #3
  srshr v1.4s, v8.4s, #3
  srshr v2.4s, v8.4s, #3
  srshr v3.4s, v8.4s, #3
  srshr v4.4s, v8.4s, #3
  srshr v5.4s, v8.4s, #3
  srshr v6.4s, v8.4s, #3
  srshr v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)030818191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200581500003003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080132500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500003003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132200202003920039997706999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03081e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8002420050150004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010502012166102003680000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010502010161062003680000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010502010161072003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050206166102003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050206167102003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050936166102003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050206166102003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050207161062003680000102004020040200402004020040
800242003914900402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050206166102003680000102004020040200402004020040
800242003915000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001050206161062003680000102004020040200402004020040