Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSHR (vector, 8B)

Test 1: uops

Code:

  srshr v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220612547251000100010003981600301830373037241432895100010001000303730371110011000073316222629100030383038303830383038
10043037220612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037236612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004303723252612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
100430372218612547251000100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037230612547251008100010003981600301830373037241432895100010001000303730371110011000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  srshr v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500000006129547251010010010000100100005004277160130018300373003728264172876310255200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000822954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500002640010362954725101001001000010010000500427716013001830037300372826432874510100204100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500001500612954725101001001000010010000500427716013001830037300372826432874510100200100002041000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500000004412954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071001611296330100001003003830038300383003830038
102043003722500000005362954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000660612954725100101010000101000050427716003001830037300372828632878510010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037224000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229689010000103003830038300383003830038
1002430037224000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037224000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
10024300372250000005362954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003722501110598612954725100101010000101000050427851203005430133300842829132876710010201000020100003003730085311002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830085300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037226000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  srshr v0.8b, v8.8b, #3
  srshr v1.8b, v8.8b, #3
  srshr v2.8b, v8.8b, #3
  srshr v3.8b, v8.8b, #3
  srshr v4.8b, v8.8b, #3
  srshr v5.8b, v8.8b, #3
  srshr v6.8b, v8.8b, #3
  srshr v7.8b, v8.8b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550123025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100022422251281231120045800001002004920049200492004920049
8020420048150006426801161008001610080028500640196020029200492004899769998680128200800382008003820048200491180201100991001008000010000022251281231120046800001002005020050200492004920049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000050208161072003680000102004020040200402004020040
80024200391500240402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000050209161062003680000102004020040200402004020040
80024200391500004025801081080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502010161082003680000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019801142080839208042220246201932180021109101080000100000050201016992003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000005020916892003680000102004020040200402004020040
800242003915000040448010710800961080104506408120200202010120039100057100198001020800002080000200922009011800211091010800001000000502091610102003680000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000050208168102003680000102004020040200402004020040
800242003915005704025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001030502010161082003680000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000050208167102003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000502010161082003680000102004020040200402004020040