Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRSRA (vector, 2S)

Test 1: uops

Code:

  srsra v0.2s, v1.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)91inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230000612548251000100010003983130301830373037241532895100010002000303730371110013021100000073116112630100030383038303830383038
10043037230000612548251000100010003983131301830373037241532895100010002000303730371110013021100000073116112630100030383038303830383038
10043037230000612548251000100010003983131301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037220000612548251000100010003983130301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037220000612548251000100010003983131301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037230000612548251000100010003983130301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037230000612548251000100010003983130301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037220000612548251000100010003983130301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037230000612548251000100010003983130301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038
10043037220000612548251000100010003983131301830373037241532895100010002000303730371110010100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  srsra v0.2s, v1.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773133001830037300372827207287401010020010008200200163003730037111020110099100100100001000011171801600296470100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372827206287401010020010008200200163003730037111020110099100100100001000011171701600296460100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020530037225061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722501274295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250631295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372251561295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000124295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000010861295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  srsra v0.2s, v0.2s, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000264147295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010002000011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830133300372825262873310100200100002002000030037300371110201100991001001000010000013011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300375110201100991001001000010000000011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000000011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000000011172222422296290100001003003830038300383003830038
10204300372250008897295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000000011172225722296290100001003003830038300383003830038
1020430134225000097295472510100100100001001000050042771603001830228300372825262873310100200100002002000030037300371110201100991001001000010000000011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000000011172222422296290100001003003830038300383003830038
1020430037225000097295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000016011172222422296290100001003003830038300383003830038
10204300372250000762295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000000011172222422296290100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037224089295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510020101000010100005042771600300183300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000704216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100100640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100100640216222962910000103003830038300383003830038
1002430037224061295476210010101000010100005042785120300180302263003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300180300373003728286328767100102010000202000030037300371110021109101010000100000640816222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra v0.2s, v8.2s, #3
  movi v1.16b, 0
  srsra v1.2s, v8.2s, #3
  movi v2.16b, 0
  srsra v2.2s, v8.2s, #3
  movi v3.16b, 0
  srsra v3.2s, v8.2s, #3
  movi v4.16b, 0
  srsra v4.2s, v8.2s, #3
  movi v5.16b, 0
  srsra v5.2s, v8.2s, #3
  movi v6.16b, 0
  srsra v6.2s, v8.2s, #3
  movi v7.16b, 0
  srsra v7.2s, v8.2s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915000000213002925801161008001610080028500640196120045200652006571280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651500000036002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000005725801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
16020420065150000000005025801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651500000042002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420051150051258001010800001080000506400000120031200502005032280010208000020160000200502005011160021109101016000010010039311202021122132004315160000102004720047200472004720047
16002420046150051258001010800001080000506400000120031200502005032280010208000020160000200502005011160021109101016000010010114622142442213182004730160000102005120051200512005120051
16002420050150051258001010800001080000506400000120031200502005032280010208000020160000200462004611160021109101016000010010037311192021112202004315160000102004720047200472004720047
16002420046150045258001010800001080000506400001120027200462004632280010208000020160000200502005011160021109101016000010010041622132442214142004730160000102005120051200512005120051
16002420050150045258001010800001080000506400001120027200462004632280010208000020160000200462004611160021109101016000010010036311132021114202004315160000102004720047200472004720047
16002420046150045258001010800001080000506400001120027200462004632280010208000020160000200462004611160021109101016000010010034321132021111112004315160000102004720047200472004720047
16002420046150045258001010800001080000506400001120027200462004632280010208000020160000200462004611160021109101016000010010036311142021115142004315160000102004720047200472004720047
16002420046150051258001010800001080000506400000120031200502005032280010208000020160000200502005011160021109101016000010010039622112442211132004730160000102005120051200512005120051
16002420050151051258001010800001080000506400000120031200502005032280010208000020160000200502005011160021109101016000010010040622102442212202004730160000102005120051200512005120051
16002420050150951258001010800001080000506400000120031200502005032280010208000020160000200502005011160021109101016000010010037311202021120152004315160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  srsra v0.2s, v16.2s, #3
  srsra v1.2s, v16.2s, #3
  srsra v2.2s, v16.2s, #3
  srsra v3.2s, v16.2s, #3
  srsra v4.2s, v16.2s, #3
  srsra v5.2s, v16.2s, #3
  srsra v6.2s, v16.2s, #3
  srsra v7.2s, v16.2s, #3
  srsra v8.2s, v16.2s, #3
  srsra v9.2s, v16.2s, #3
  srsra v10.2s, v16.2s, #3
  srsra v11.2s, v16.2s, #3
  srsra v12.2s, v16.2s, #3
  srsra v13.2s, v16.2s, #3
  srsra v14.2s, v16.2s, #3
  srsra v15.2s, v16.2s, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400602990003025160108100160008100160020500128013210400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101185101600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013215400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013215400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013210400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013215400204003940039199896199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
1602044003930011503025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013215400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180101600400361600001004004040040400404004040040
1602044003929901803025160108100160008100160020500128013210400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
1602044003929900020125160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013215400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000111101180001600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930000000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002313111316221261740036206160000104004040040400404004040040
160024400392990000046251600101016000010160000501280788111040020400394003919996320019160010201600002032000040039400391116002110910101600001000000100233112616211132440036206160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002313112316211262440036206160000104004040040400404004040040
1600244003930000000522516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002313612616211132440036206160000104004040040400404004040040
16002440039300000301021251600101016000010160000501280000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002313112616211112440036206160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000031002213612416211122440036206160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002213612416211122440036206160000104004040040400404004040040
160024400393000000067251600101016000010160000501280000110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002313612416211242440036206160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002213611216211221040036206160000104004040040400404004040040
1600244003929910000462516001010160000101600005012800001104002040039400391999632001916001020160000203200004003940039111600221091010160000100000010024167111164212410400362012160000104004040040400404004040040