Firestorm: SRSRA (vector, 8B) measurements

Code:

  srsra v0.8b, v1.8b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3085
1004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	0	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  srsra v0.8b, v1.8b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	a9	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	232	0	0	0	0	0	0	8678	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	22	28904	12251	230	11492	230	22648	30419	30607	13	1	10201	100	99	100	100	10000	100	0	0	0	0	0	2	958	0	2	83	1	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30085	232	0	1	11	8	1320	704	61	29440	200	10201	151	10064	163	10298	718	4289526	0	30342	30659	30363	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	25235	0	710	0	1	16	1	2	29993	40	10000	100	30470	30468	30561	30693	30470
10204	30513	236	1	0	0	0	12	0	3933	29512	83	10164	100	10024	134	10745	676	4282741	0	30198	30231	30227	28283	22	28837	10874	212	10831	214	21656	30274	30226	5	1	10201	100	99	100	100	10000	100	0	0	2	4	21905	0	823	0	2	56	2	1	29741	19	10000	100	30227	30180	30230	30181	30234
10204	30178	282	1	0	4	4	672	352	6664	29503	188	10199	150	10056	126	10447	686	4280027	0	30126	30136	30178	28274	19	28800	10423	208	10167	208	20334	30181	30133	3	1	10201	100	99	100	100	10000	100	0	1	0	0	3	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	238	0	0	0	0	0	0	183	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30325
10024	30367	227	0	1	1	7	7	939	616	5039	29485	161	10062	13	10048	16	10894	66	4285455	1	30270	30366	30367	28310	32	28884	11060	22	10661	22	21938	30319	30365	8	1	10021	10	9	10	10	10000	10	0	2	0	0	2	2968	2	0	786	6	72	4	4	29882	3	10000	10	30368	30369	30372	30359	30368
10024	30368	228	1	0	1	6	8	933	176	4632	29494	161	10069	15	10048	13	10894	65	4286651	1	30234	30368	30368	28313	34	28900	11059	24	11157	22	21944	30274	30320	8	1	10021	10	9	10	10	10000	10	2	0	2	4	2	19258	4	0	766	4	105	4	6	29882	1	10000	10	30369	30368	30370	30373	30181
10024	30367	228	1	1	1	7	7	924	440	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	2	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30085
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  srsra v0.8b, v0.8b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	241	0	0	0	0	0	0	0	276	29547	25	10100	100	10000	100	10000	500	4277160	0	30054	0	30037	30037	28271	7	28741	10100	200	10176	206	20016	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	1	29646	0	10000	100	30038	30086	30038	30038	30038
10204	30085	241	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	147	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	2	24	2	2	29736	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	3479	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	5	2	0	0	1	1	1	718	0	17	2	2	29629	1	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	0	0	0	1327	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	2	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	18	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	273	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	4	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	145	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	145	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	440	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	468	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28785	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	5	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30086	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra v0.8b, v8.8b, #3
  movi v1.16b, 0
  srsra v1.8b, v8.8b, #3
  movi v2.16b, 0
  srsra v2.8b, v8.8b, #3
  movi v3.16b, 0
  srsra v3.8b, v8.8b, #3
  movi v4.16b, 0
  srsra v4.8b, v8.8b, #3
  movi v5.16b, 0
  srsra v5.8b, v8.8b, #3
  movi v6.16b, 0
  srsra v6.8b, v8.8b, #3
  movi v7.16b, 0
  srsra v7.8b, v8.8b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	12	29	25	80116	100	80121	100	80028	500	640196	0	20045	0	20158	20065	6	33	80234	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	18	310	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80450	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	297	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	12	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80136	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	42	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20126	150	0	156	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20050	20046	3	22	80010	20	80000	20	160000	20181	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	10	20	32	1	1	5	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	8	20	31	2	1	5	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	3	1	1	7	20	27	2	1	8	5	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	5	20	35	2	1	9	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	325	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	8	20	27	2	1	5	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10058	6	2	2	9	122	21	2	2	8	5	20047	15	0	0	160000	10	20051	20047	20047	20051	20051
160024	20050	151	0	114	25	80010	10	80000	10	80000	50	640000	0	1	0	20031	20050	20050	3	22	80010	20	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	6	2	2	8	24	23	2	2	9	8	20047	15	0	0	160000	10	20047	20047	20051	20047	20047
160024	20050	150	0	51	25	80010	10	80000	10	80000	50	640000	0	1	0	20031	20046	20050	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	5	20	31	2	1	8	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	161	0	213	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20127	1	1	160021	10	9	10	10	160000	10	2	0	0	10031	3	1	1	5	20	31	1	1	5	8	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	8	20	29	1	1	8	5	20043	15	0	0	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  srsra v0.8b, v16.8b, #3
  srsra v1.8b, v16.8b, #3
  srsra v2.8b, v16.8b, #3
  srsra v3.8b, v16.8b, #3
  srsra v4.8b, v16.8b, #3
  srsra v5.8b, v16.8b, #3
  srsra v6.8b, v16.8b, #3
  srsra v7.8b, v16.8b, #3
  srsra v8.8b, v16.8b, #3
  srsra v9.8b, v16.8b, #3
  srsra v10.8b, v16.8b, #3
  srsra v11.8b, v16.8b, #3
  srsra v12.8b, v16.8b, #3
  srsra v13.8b, v16.8b, #3
  srsra v14.8b, v16.8b, #3
  srsra v15.8b, v16.8b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	620	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40069	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	4	2	0	2	1250	2	10022	3	1	1	20	16	2	1	1	10	21	40151	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	67	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	9	16	2	1	2	21	10	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	0	10022	3	1	1	18	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	711	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	9	16	2	1	1	8	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	236	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	3	0	46	25	160010	10	160098	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40062	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	9	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	20	40036	0	20	6	160000	10	40040	40040	40040	40040	40040

SRSRA (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations