Firestorm: SRSRA (vector, 8H) measurements

Code:

  srsra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	105	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	267	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  srsra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28762	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	432	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	21	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	192	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	933	0	81	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	693	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	756	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	29630	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	552	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30085	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	29630	0	1	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  srsra v0.8h, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	0	1	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	1	16	1	1	29650	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277618	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	1	1	1	717	1	16	1	1	29649	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	4	24	4	4	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	4	24	4	3	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	722	4	24	3	4	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	1	24	4	4	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	4	24	4	3	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	3	24	1	4	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	268	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	722	4	24	3	4	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	1	1	1	722	4	24	3	4	29629	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	8	28786	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	24	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10025	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	8	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra v0.8h, v8.8h, #3
  movi v1.16b, 0
  srsra v1.8h, v8.8h, #3
  movi v2.16b, 0
  srsra v2.8h, v8.8h, #3
  movi v3.16b, 0
  srsra v3.8h, v8.8h, #3
  movi v4.16b, 0
  srsra v4.8h, v8.8h, #3
  movi v5.16b, 0
  srsra v5.8h, v8.8h, #3
  movi v6.16b, 0
  srsra v6.8h, v8.8h, #3
  movi v7.16b, 0
  srsra v7.8h, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	3	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	276	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	47	3	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	694	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	6	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	0	0	3	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10042	6	2	2	0	29	26	3	2	2	19	31	20049	31	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	1	0	0	0	1	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10058	6	2	2	0	32	26	3	2	2	19	28	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	1	0	0	0	0	1	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10058	6	2	2	0	31	26	3	2	2	32	32	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	1	2	0	0	0	0	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10054	3	1	1	0	31	20	2	1	1	29	31	20043	15	0	160000	10	20047	20047	20047	20047	20053
160024	20053	150	0	0	1	0	0	0	1	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10047	6	2	2	1	33	26	3	2	2	26	33	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20053	150	1	0	2	0	0	0	0	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10057	6	2	2	0	34	27	3	2	2	32	32	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20053	150	1	1	1	0	0	0	1	63	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10061	6	2	2	1	34	26	3	2	2	33	26	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	0	2	0	0	348	0	51	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10058	6	2	2	1	35	26	3	2	2	33	34	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	1	1	0	0	0	0	51	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20050	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10058	6	2	2	0	33	26	3	2	2	34	33	20049	31	0	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	1	1	0	0	0	0	51	25	80010	10	80000	10	80000	50	640000	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10052	6	2	2	1	30	26	3	2	2	32	34	20049	31	0	160000	10	20053	20053	20053	20053	20053

Test 5: throughput

Count: 16

Code:

  srsra v0.8h, v16.8h, #3
  srsra v1.8h, v16.8h, #3
  srsra v2.8h, v16.8h, #3
  srsra v3.8h, v16.8h, #3
  srsra v4.8h, v16.8h, #3
  srsra v5.8h, v16.8h, #3
  srsra v6.8h, v16.8h, #3
  srsra v7.8h, v16.8h, #3
  srsra v8.8h, v16.8h, #3
  srsra v9.8h, v16.8h, #3
  srsra v10.8h, v16.8h, #3
  srsra v11.8h, v16.8h, #3
  srsra v12.8h, v16.8h, #3
  srsra v13.8h, v16.8h, #3
  srsra v14.8h, v16.8h, #3
  srsra v15.8h, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	299	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	1	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	132	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40088
160204	40039	299	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	505	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40086	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	64	26	160116	100	160016	100	160028	500	1280196	40029	40049	40048	19976	9	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10129	1	23	1	1	40045	160000	100	40049	40049	40050	40049	40049
160204	40048	300	0	0	64	26	160116	100	160016	100	160028	500	1280196	40029	40048	40048	19976	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10128	1	23	1	1	40046	160000	100	40049	40049	40049	40049	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	8	16	2	1	1	3	10	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	217	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320280	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	3	16	2	1	1	3	9	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	5	9	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	4	7	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	5	7	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	5	8	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	167	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	3	16	2	1	1	6	7	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	1	10022	3	1	1	3	16	2	1	1	5	11	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	4	16	2	1	1	5	6	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	6	16	2	1	1	5	6	40036	15	5	160000	10	40040	40040	40040	40040	40040

SRSRA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations