Firestorm: SRSRA (vector, D) measurements

Code:

  srsra d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	9	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	15	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	251	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  srsra d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28762	10274	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	33	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	21	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	93	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	138	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	99	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28287	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	69	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	114	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	210	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	120	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	12	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	189	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	135	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30084	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	12	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	12	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	4	661	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	192	0	783	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	9	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10008	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  srsra d0, d0, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	50	3	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	32	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30054	3	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	33	99	1	1	1	718	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	1	1	1	717	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	63	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	53	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	35	0	1	1	1	718	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1141	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	44	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	44	3	1	1	1	718	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	30	3	1	1	1	718	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	41	0	1	1	1	718	16	29646	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	38	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	227	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	33	6	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	41	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	36	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	35	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	21	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	44	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	45	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	47	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	45	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra d0, d8, #3
  movi v1.16b, 0
  srsra d1, d8, #3
  movi v2.16b, 0
  srsra d2, d8, #3
  movi v3.16b, 0
  srsra d3, d8, #3
  movi v4.16b, 0
  srsra d4, d8, #3
  movi v5.16b, 0
  srsra d5, d8, #3
  movi v6.16b, 0
  srsra d6, d8, #3
  movi v7.16b, 0
  srsra d7, d8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	2	0	9	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	24	1	1	1	10119	0	16	1	1	20074	160000	100	20079	20078	20078	20078	20079
160204	20077	150	0	0	0	65	30	80119	100	80019	100	80031	500	640220	0	20056	20077	20078	10	12	80131	200	80031	200	160062	20077	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10131	1	23	1	1	20074	160000	100	20078	20078	20078	20078	20078
160204	20077	150	0	0	0	65	29	80119	100	80019	100	80031	500	640220	0	20056	20078	20077	9	12	80131	200	80031	200	160062	20077	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10131	1	23	1	1	20074	160000	100	20078	20078	20079	20078	20078
160204	20077	150	0	0	0	65	30	80119	100	80019	100	80031	500	640220	1	20056	20077	20078	10	12	80131	200	80031	200	160062	20077	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10131	1	23	1	1	20074	160000	100	20079	20079	20078	20079	20079
160204	20077	150	0	0	0	65	30	80119	100	80019	100	80031	500	640220	0	20056	20077	20078	9	12	80131	200	80031	200	160062	20077	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	3	2	2	2	10130	1	23	1	1	20075	160000	100	20078	20078	20078	20078	20078
160204	20078	150	0	0	39	65	29	80119	100	80019	100	80031	500	640220	0	20056	20077	20078	9	12	80131	200	80031	200	160062	20077	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10130	1	23	1	1	20075	160000	100	20078	20078	20078	20079	20079

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20077	150	0	0	12	710	27	80010	10	80000	10	80000	50	640000	1	1	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	11	2	2	11	25	2	1	1	9	5	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20060	150	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10036	3	4	1	6	34	2	1	1	14	9	20048	20	1	160000	10	20052	20052	20052	20061	20074
160024	20051	150	0	0	0	45	27	80115	10	80000	10	80000	50	640832	1	0	0	20032	20051	20051	11	22	80010	20	80105	20	160000	20060	20051	1	1	160021	10	9	10	10	160000	10	6	6	0	10032	8	4	1	5	25	2	1	1	6	9	20048	20	1	160000	10	20061	20061	20052	20052	20065
160024	20051	151	0	1	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	5	2	10	25	2	2	2	7	9	20048	40	2	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	4	1	6	25	2	1	1	8	9	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	0	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	4	1	7	25	2	1	1	10	5	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	5	0	0	10031	8	4	1	5	25	2	1	1	10	14	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	0	87	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	4	2	9	25	2	1	1	13	13	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10037	11	4	1	14	25	2	1	1	8	5	20048	20	1	160000	10	20052	20052	20052	20052	20065
160024	20051	150	0	0	12	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	8	5	1	7	25	2	2	1	5	11	20048	20	1	160000	10	20061	20052	20061	20052	20065

Test 5: throughput

Count: 16

Code:

  srsra d0, d16, #3
  srsra d1, d16, #3
  srsra d2, d16, #3
  srsra d3, d16, #3
  srsra d4, d16, #3
  srsra d5, d16, #3
  srsra d6, d16, #3
  srsra d7, d16, #3
  srsra d8, d16, #3
  srsra d9, d16, #3
  srsra d10, d16, #3
  srsra d11, d16, #3
  srsra d12, d16, #3
  srsra d13, d16, #3
  srsra d14, d16, #3
  srsra d15, d16, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	10	3	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	49	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	29	9	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	28	6	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	30	12	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	32	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	8	6	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	3	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	201	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	2	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	4	3	3	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	1	1	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	30	3	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	29	0	3	0	0	10022	3	2	2	4	16	2	2	1	5	5	40036	15	5	160000	10	40970	40196	40040	40080	40040
160024	40039	324	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40191	40300	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	9	0	0	0	0	10022	3	1	2	5	16	2	2	2	4	5	40036	15	5	160000	10	40040	40040	40040	40064	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	0	10024	6	2	2	4	16	4	2	2	4	4	40036	15	10	160000	10	40040	40090	40090	40067	40040
160024	40039	300	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	2	0	36	0	0	0	0	10022	6	2	2	4	16	2	2	2	4	4	40036	30	5	160000	10	40040	40040	40040	40064	40040
160024	40039	300	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	68	0	0	0	0	10024	6	2	1	4	16	4	2	2	5	5	40036	30	5	160000	10	40040	40040	40040	40064	40040
160024	40039	300	0	0	0	0	0	0	839	25	160010	10	160000	10	160104	50	1280000	1	1	40020	40039	40039	19996	7	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10	0	15	0	0	10024	6	2	2	8	16	4	2	2	4	7	40036	15	10	160000	10	40040	40040	40040	40060	40040
160024	40039	299	0	0	0	0	4	0	52	171	160107	10	160000	10	160000	50	1280776	0	1	40020	40039	40195	19996	3	20019	160114	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	7	0	6	0	0	10022	3	1	1	5	16	2	1	1	5	5	40036	15	5	160000	10	40040	40040	40040	40064	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	18	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	6	0	3	0	0	10022	3	1	1	4	16	2	1	1	5	5	40036	15	5	160000	10	40040	40040	40040	40063	40107
160024	40039	300	1	0	0	0	0	0	519	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40664	40039	19996	3	20019	160010	20	160310	20	320208	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	22	0	0	0	0	10024	6	2	2	5	16	4	2	2	5	8	40036	30	10	160000	10	40040	40040	40040	40066	40040
160024	40039	300	0	0	0	0	0	39	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	0	0	10022	3	1	1	4	16	2	1	1	5	5	40036	15	5	160000	10	40040	40040	40040	40059	40040

SRSRA (vector, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations