Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSHLL2 (8H)

Test 1: uops

Code:

  sshll2 v0.8h, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371661168625100010001000264521020182037203715713189510001000100020372037111001100001873116111786100020382038203820382038
10042037156116862510001000100026452102018203720371571318951000100010002037203711100110001073116111786100020382038203820382038
10042037166116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037166116862510001000100026452102018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
10042037166116862510001000100026452112018203720371571318951000100010002037203711100110001073116111786100020382038203820382038
10042037166116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037156116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037166116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037166116862510001000100026452112018203720371571318951000100010002037203711100110000973116111786100020382038203820382038
10042037156116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sshll2 v0.8h, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000002051968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000100071011611197910100001002003820038200382003820038
102042003715500907261968625101001001000010010000500284752102005420037200371842103187971010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000002101968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037211020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752112001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000001031968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150007119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200841844331876710010201000020100002003720037111002110910101000010000001476402162219786010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100002006404162219786010000102003820038200382003820038
1002420037149006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100001006402162219786010000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000126402162219786010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100001006402162219786010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100001006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sshll2 v0.8h, v8.16b, #3
  sshll2 v1.8h, v8.16b, #3
  sshll2 v2.8h, v8.16b, #3
  sshll2 v3.8h, v8.16b, #3
  sshll2 v4.8h, v8.16b, #3
  sshll2 v5.8h, v8.16b, #3
  sshll2 v6.8h, v8.16b, #3
  sshll2 v7.8h, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
80204200381500004380029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039
802042003815000060086258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000000000011151180160200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010004502000216532003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820062118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010030502000216322003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502000216232003580000102003920039200392003920039
800242003815039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502000216222003580000102003920039200392003920039
800242003815039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502000216322003580000102003920039200392003920039