Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSHL (vector, 2S)

Test 1: uops

Code:

  sshl v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371611002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715117202681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371611002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
100420371511002681687251000100010002646800201820372037157231895100010002000203720371110011000077416441787100020382038203820382038

Test 2: Latency 1->2

Code:

  sshl v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000005200071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000100071011611198490100001002003820038200382003820083
10204200371500061196872510100100100001001000050028476800200182003720037184220318745102562001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500126311968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000000057071011611197910100001002003820038200382003820038
102042003715010124196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000052228476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000009001031968725100101010000101000050284768012001820037200371844481878610010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000001500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000306402162219785010000102003820038200382003820038
100242003715000000005601968725100101010012101000050284768012001820085200371844431876710010201016820204602008420037111002110910101000010000012006402162219785010000102003820038200382003820038
100242003715000001800611968725100101010000101000050284768012001820037200831844431878610166201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000821968725100101010000101000050284768012006520037200371844431876710010201000020200002003720037111002110910101000010000000306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sshl v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000240389196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000015071011611197910100001002003820038200382003820038
102042003714900000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000015071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000306119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000213071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785110000102003820038200382003820038
1002420037150001561968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150024611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500252611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500252611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sshl v0.2s, v8.2s, v9.2s
  sshl v1.2s, v8.2s, v9.2s
  sshl v2.2s, v8.2s, v9.2s
  sshl v3.2s, v8.2s, v9.2s
  sshl v4.2s, v8.2s, v9.2s
  sshl v5.2s, v8.2s, v9.2s
  sshl v6.2s, v8.2s, v9.2s
  sshl v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110521611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000305110511611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200382180201100991001008000010000481685110511611200350800001002003920039200392003920039
802042003815000000822580100100800001008000050064000010200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110521611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110511611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000105110511611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400001520019200382003899733999680100200800002001600002003820038118020110099100100800001000001355110511611200350800001002003920039200392003920039
802042003814900000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110511611200350800001002003920039200392003920039
8020420038150000009625801001008000010080000500640000152001920038200389973310030801002008000020016000020038200381180201100991001008000010000005110511611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000005110511611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss instruction (0a)18193f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfl1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150100039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502001416141720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502111716171820035080000102003920039200392003920039
800242003815010003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000050211916171420035080000102003920039200392003920039
8002420038150100039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502001716171720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502001716171720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502001716171720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010100502001416151720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502001416171420035080000102003920039200392003920039
8002420038150000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010100502001816101720035080000102003920039200392003920039
800242003815000003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000050200161691620035080000102003920039200392003920039