Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSHL (vector, 4S)

Test 1: uops

Code:

  sshl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371500156168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371500611687251000100010002646801201820372037157231913100010002000203720372110011000001273216221787100020382038203820382038
100420371500291168725101210001000264680120182037203715768189510001000200020372037111001100000073216221787100020382038203820382038
100420371510611687251000100010002646801201820372037157231895100010002000203720371110011000001273216221787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000673216221787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037160061168725100010001000264680020182037203715723189510001000200020372037111001100000673216221787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  sshl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000008219687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000002000071011611197910100001002003820038200382003820038
102042008515000000108060719687491012010010000100100005002847680200182003720037184223187451010020010000200200002008620037111020110099100100100001000000400071011611197910100001002003820038200382003820038
1020420037150000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000051000071011611197910100001002003820038200382003820038
1020420037150000000010319687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000120023219687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000030071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000009006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000002000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)030918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010162202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000001031968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715001000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000306402162219785010000102003820038200382003820038
100242003715000000611968725100101010012101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000306402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010169202033620084200842110021109101010000104000383526623242319823110000102008620086201342008520085

Test 3: Latency 1->3

Code:

  sshl v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000710116111979118100001002003820038200382003820038
102042003715000000074419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000081319687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000073519687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000065019687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500145196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640224221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037150084196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sshl v0.4s, v8.4s, v9.4s
  sshl v1.4s, v8.4s, v9.4s
  sshl v2.4s, v8.4s, v9.4s
  sshl v3.4s, v8.4s, v9.4s
  sshl v4.4s, v8.4s, v9.4s
  sshl v5.4s, v8.4s, v9.4s
  sshl v6.4s, v8.4s, v9.4s
  sshl v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420047150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000069904025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000051004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000061025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011612200350800001002003920039200392003920039
8020420038150000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500024425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502415160151720035080000102003920039200392003920039
8002420038150002442580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050249160161320035080000102003920039200392003920039
8002420038150056424425800101080000108000050640000200192003820038999631001880010208039020160000200382003811800211091010800001000000502412160121620035080000102003920039200392003920039
8002420038150002442580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050241616015820035080000102003920039200392003920039
80024200381500024425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502417160161720035080000102003920039200392003920039
80024200381500024425800101080092108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000100502416160171520077080000102003920039200392003920039
800242003815001224425800101080095108000066640000200192003820038999631004580010208000020160000200382003831800211091010800001000000502412160151420035080000102003920039200392003920039
80024200381500024425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502411160151620035080000102003920039200392003920039
80024200381500024425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502415160161620035080000102003920039200392003920039
8002420038150059424425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502418160161720035080000102003920039200392003920039