Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSHL (vector, 8B)

Test 1: uops

Code:

  sshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073216231785100020382038203820382038
10042037150611687251000100010002646801201820372037157331895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216331787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000075216231785100020382038203820382038
100420371602321687251000100010002646800201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037160611687251000100010002646801201820372037157231895100010002000203720371110011000075216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  sshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476800200182003720037184296187411010020010008200200162003720037111020110099100100100001000001117170160019802100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184427187411010020010008200200162003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000103196872510100100100001001000052228476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000124196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000145196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150243719687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100064410161051978510000102003820038200382003820038
100242003715026619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100064410165101978510000102003820038200382003820038
1002420037150266196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038
10024200371502661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010615644101610111978510000102003820038200382003820038
100242003715026619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100064410161081978510000102003820038200382003820038
1002420037150266196766110023101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038
1002420037150266196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038
1002420037150266196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038
1002420037150266196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038
1002420037150266196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000644101610101978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sshl v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715041161196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715047161196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150089196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715024361196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715048661196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000307101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640316221978510000102003820038200382003820038
1002420037150917661196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371490061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sshl v0.8b, v8.8b, v9.8b
  sshl v1.8b, v8.8b, v9.8b
  sshl v2.8b, v8.8b, v9.8b
  sshl v3.8b, v8.8b, v9.8b
  sshl v4.8b, v8.8b, v9.8b
  sshl v5.8b, v8.8b, v9.8b
  sshl v6.8b, v8.8b, v9.8b
  sshl v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511031611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511021611200350800001002003920039200392003920039
80204200381500000000034825801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011621200350800001002003920039200392003920039
8020420038151000000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)daddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150534039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001001000502026160272720035080000102003920039200392003920039
8002420038150357039258001010800001080000506400000200192003820087999631001880010208000020160000200382003811800211091010800001000000502016270271120035080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015160271420035080000102003920039200392003920039
800242003815024039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000502024160142720035080000102003920039200392003920039
80024200381500239258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000502027160202720035080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502020160271620035080000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000502026160272620035080000102003920039200392003920039
8002420038150267039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000502027160272720035080000102003920039200392003920039
80024200381500060258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000502020160262220035080000102003920039200392003920039
80024200381500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000030502027160272720035080000102003920039200392003920039