Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
sshr v0.2s, v0.2s, #3
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 1 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 82 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 126 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 16 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 21 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 16 | 0 | 15 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1107 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 1 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 1 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 61 | 1686 | 25 | 1000 | 1000 | 1000 | 264521 | 0 | 2018 | 2037 | 2037 | 1571 | 3 | 1895 | 1000 | 1000 | 1000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1786 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
Code:
sshr v0.2s, v0.2s, #3
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | ld unit uop (a6) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 20037 | 150 | 2 | 0 | 0 | 0 | 69 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 1 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 6 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 3 | 0 | 0 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 735 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 536 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 42 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 22 | 10000 | 100 | 20087 | 20038 | 20038 | 20038 | 20038 |
10204 | 20085 | 150 | 0 | 1 | 0 | 0 | 0 | 0 | 650 | 19675 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 204 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20087 | 20086 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 1 | 0 | 0 | 4 | 12 | 108 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 1 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 2 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 0 | 20018 | 20037 | 20037 | 18421 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 10000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 20037 | 150 | 66 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 2 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 6 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 27 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18450 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 33 | 82 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10162 | 20 | 10000 | 20 | 10000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
Count: 8
Code:
sshr v0.2s, v8.2s, #3 sshr v1.2s, v8.2s, #3 sshr v2.2s, v8.2s, #3 sshr v3.2s, v8.2s, #3 sshr v4.2s, v8.2s, #3 sshr v5.2s, v8.2s, #3 sshr v6.2s, v8.2s, #3 sshr v7.2s, v8.2s, #3
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2506
retire uop (01) | cycle (02) | 03 | 18 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80204 | 20048 | 150 | 0 | 57 | 29 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 0 | 0 | 20019 | 20038 | 20038 | 9977 | 0 | 6 | 9989 | 80120 | 200 | 80032 | 200 | 80032 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 1 | 1 | 1 | 5118 | 0 | 0 | 0 | 16 | 0 | 0 | 20035 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
80204 | 20038 | 150 | 0 | 180 | 29 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 0 | 0 | 20019 | 20038 | 20038 | 9977 | 0 | 6 | 9989 | 80120 | 200 | 80032 | 200 | 80032 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 1 | 1 | 1 | 5118 | 0 | 0 | 0 | 16 | 0 | 0 | 20035 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
80204 | 20038 | 150 | 0 | 0 | 409 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 0 | 20019 | 20038 | 20038 | 9977 | 0 | 6 | 9989 | 80120 | 200 | 80032 | 200 | 80032 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 1 | 1 | 1 | 5118 | 0 | 0 | 0 | 16 | 0 | 0 | 20035 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
80204 | 20038 | 150 | 0 | 0 | 29 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 0 | 20019 | 20038 | 20038 | 9977 | 0 | 6 | 9989 | 80120 | 200 | 80032 | 200 | 80032 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 1 | 1 | 1 | 5118 | 0 | 0 | 0 | 16 | 0 | 0 | 20035 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
80204 | 20038 | 150 | 0 | 0 | 64 | 26 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 0 | 20028 | 20048 | 20049 | 9976 | 0 | 9 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20048 | 20049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5128 | 0 | 0 | 1 | 23 | 1 | 1 | 20045 | 80000 | 100 | 20050 | 20049 | 20049 | 20049 | 20050 |
80204 | 20048 | 150 | 0 | 12 | 64 | 27 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 0 | 20028 | 20048 | 20049 | 9976 | 0 | 9 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20048 | 20048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5128 | 0 | 0 | 1 | 23 | 1 | 1 | 20045 | 80000 | 100 | 20049 | 20049 | 20049 | 20049 | 20049 |
80204 | 20048 | 150 | 0 | 0 | 85 | 26 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 0 | 20028 | 20049 | 20048 | 9976 | 7 | 10 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20048 | 20049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5129 | 0 | 0 | 1 | 23 | 1 | 1 | 20046 | 80000 | 100 | 20049 | 20050 | 20049 | 20049 | 20049 |
80204 | 20048 | 150 | 0 | 0 | 729 | 27 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 0 | 0 | 20028 | 20049 | 20048 | 9976 | 0 | 9 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20048 | 20048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5128 | 0 | 0 | 1 | 23 | 1 | 1 | 20045 | 80000 | 100 | 20050 | 20049 | 20049 | 20049 | 20049 |
80204 | 20048 | 150 | 0 | 0 | 64 | 27 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 0 | 0 | 20028 | 20048 | 20048 | 9976 | 0 | 10 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20049 | 20048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5128 | 0 | 0 | 1 | 23 | 1 | 1 | 20045 | 80000 | 100 | 20049 | 20049 | 20049 | 20050 | 20049 |
80204 | 20048 | 150 | 0 | 0 | 64 | 27 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 0 | 0 | 20028 | 20049 | 20049 | 9976 | 0 | 9 | 9986 | 80128 | 200 | 80038 | 200 | 80038 | 20049 | 20048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 2 | 2 | 2 | 5129 | 0 | 0 | 1 | 23 | 1 | 1 | 20045 | 80000 | 100 | 20049 | 20050 | 20050 | 20050 | 20050 |
Result (median cycles for code divided by count): 0.2505
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | c2 | cd | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80024 | 20051 | 150 | 0 | 0 | 0 | 0 | 0 | 33 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80108 | 50 | 640000 | 0 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 5 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
80024 | 20038 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 5 | 16 | 3 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
80024 | 20038 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 4 | 16 | 4 | 4 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
80024 | 20038 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 4 | 16 | 4 | 3 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
80024 | 20038 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 2 | 16 | 4 | 4 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
80024 | 20038 | 150 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 80000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 4 | 16 | 4 | 3 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
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