Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSHR (vector, 2S)

Test 1: uops

Code:

  sshr v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150082168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715012661168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600611686251000100010002645210201820372037157131895100010001000203720371110011000002173116111786100020382038203820382038
100420371601561168625100010001000264521020182037203715713189510001107100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sshr v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371502000690611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000060611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150003000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000073511611197910100001002003820038200382003820038
1020420037150000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500000005361968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000004206119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000710116111979122100001002008720038200382003820038
10204200851500100006501967525101001001000010010000500284752102001820037200371842131874510100200100002041000020037200371110201100991001001000010000071011611197910100001002008720086200382003820038
1020420037150100412108611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010020071011611197910100001002003820038200382003820038
1020420037150000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715066611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786210000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371506611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
100242003715027611968625100101010000101000050284752120018200372003718450318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
10024200371500611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038
100242003715033821968625100101010000101000050284752120018200372003718443318767101622010000201000020037200371110021109101010000100006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sshr v0.2s, v8.2s, #3
  sshr v1.2s, v8.2s, #3
  sshr v2.2s, v8.2s, #3
  sshr v3.2s, v8.2s, #3
  sshr v4.2s, v8.2s, #3
  sshr v5.2s, v8.2s, #3
  sshr v6.2s, v8.2s, #3
  sshr v7.2s, v8.2s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420048150057292580108100800081008002050064013200200192003820038997706998980120200800322008003220038200381180201100991001008000010001115118000160020035800001002003920039200392003920039
80204200381500180292580108100800081008002050064013200200192003820038997706998980120200800322008003220038200381180201100991001008000010001115118000160020035800001002003920039200392003920039
8020420038150004092580108100800081008002050064013210200192003820038997706998980120200800322008003220038200381180201100991001008000010001115118000160020035800001002003920039200392003920039
802042003815000292580108100800081008002050064013210200192003820038997706998980120200800322008003220038200381180201100991001008000010001115118000160020035800001002003920039200392003920039
802042003815000642680116100800161008002850064019610200282004820049997609998680128200800382008003820048200491180201100991001008000010002225128001231120045800001002005020049200492004920050
8020420048150012642780116100800161008002850064019610200282004820049997609998680128200800382008003820048200481180201100991001008000010002225128001231120045800001002004920049200492004920049
8020420048150008526801161008001610080028500640196102002820049200489976710998680128200800382008003820048200491180201100991001008000010002225129001231120046800001002004920050200492004920049
8020420048150007292780116100800161008002850064019600200282004920048997609998680128200800382008003820048200481180201100991001008000010002225128001231120045800001002005020049200492004920049
8020420048150006427801161008001610080028500640196002002820048200489976010998680128200800382008003820049200481180201100991001008000010002225128001231120045800001002004920049200492005020049
802042004815000642780116100800161008002850064019600200282004920049997609998680128200800382008003820049200481180201100991001008000010002225129001231120045800001002004920050200502005020050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000000330392580010108000010801085064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200316552003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200516352003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200416442003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200416432003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216442003580000102003920039200392003920039
800242003815000000150392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200416432003580000102003920039200392003920039
80024200381500000030392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200316332003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000004050360328442007580000102008920088200982008920102
80024200881510111115010426843801031080093108009950640768120059201452014610004121004280108208009620800982008720136318002110910108000010223006800050370528552007380000102003920039200392003920039
800242003815000003360812580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200516552003580000102003920039200392003920039