Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

SSHR (vector, 4S)

Test 1: uops

Code:

  sshr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03181e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715066116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110001373116111786100020382038203820382038
1004203715008416862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150276116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715096116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sshr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)03080b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a7a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102042003715000000061196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000000103196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718421031874510100200100002001000020037200371110201100991001001000010000010123071011611197910100001002003820038200382003820038
102042003715000000061196862510100120100121001000050028475211200182003720037184210318745101002001016620010000200372003711102011009910010010000100000230126071012511197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000100071011611197910100001002003820038200382003820038
1020420037150000000103196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000003461968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000001075071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000000126196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000100071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475210200182003720037184210318745101002001000020010000200372003711102011009910010010000100000003071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)03080a18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000306406166619786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000006406166419786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100001206406165619786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000306405166519786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000006404165619786010000102003820038200382003820038
10024200371500000007261968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000906405165519786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000006405166619786010000102003820038200382003820038
1002420037149000000611968625100231010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000006406165619786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000006406166519786010000102003820038200382003820038
100242003715000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000012606406166619786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sshr v0.4s, v8.4s, #3
  sshr v1.4s, v8.4s, #3
  sshr v2.4s, v8.4s, #3
  sshr v3.4s, v8.4s, #3
  sshr v4.4s, v8.4s, #3
  sshr v5.4s, v8.4s, #3
  sshr v6.4s, v8.4s, #3
  sshr v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0304070a1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200571501113329258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151181161120035800001002003920039200392003920039
80204200381500110292580108100800081008002050064013212001920038200389977069989801202008003220080032200382003811802011009910010080000100240311151181162120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151181161120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151181161120035800001002003920039200392003920039
80204200381500110502580108100800081008002050064013202001920038200389977069989801202008003220080032200382003811802011009910010080000100210011151181161120035800001002003920039200392003920039
802042003815001102925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000012011151181161120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151181161120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010010011151181161120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000311151181161120035800001002003920039200392003920039
8020420038150011029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accfd5d6daddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80024200401500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100050203160222003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100050203160322003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000101350202160222003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100350203160322003580000102003920039200392003920039
80024200381501039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100050203160332003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001052050203160232003580000102008820039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100050204160332003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000101050202160232003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100350203160222003580000102003920039200392003920039
80024200381500039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100050203160322003580000102003920039200392003920039