Firestorm: SSRA (vector, 2S) measurements

Code:

  ssra v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	6	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	12	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	12	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  ssra v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30230	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	251	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30181	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10149	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	1	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	102	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	27	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	6	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	78	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	96	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	24	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	30	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	21	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	75	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	24	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  ssra v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	15	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	0	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	642	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	3	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30084	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	84	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	6	6	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29701	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	6	7	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ssra v0.2s, v8.2s, #3
  movi v1.16b, 0
  ssra v1.2s, v8.2s, #3
  movi v2.16b, 0
  ssra v2.2s, v8.2s, #3
  movi v3.16b, 0
  ssra v3.2s, v8.2s, #3
  movi v4.16b, 0
  ssra v4.2s, v8.2s, #3
  movi v5.16b, 0
  ssra v5.2s, v8.2s, #3
  movi v6.16b, 0
  ssra v6.2s, v8.2s, #3
  movi v7.16b, 0
  ssra v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	0	71	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	1	16	0	20105	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20167	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	3033	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	504	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20132	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	156	0	0	0	0	0	114	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20243	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	11	3	1	32	25	4	2	2	9	6	20057	0	40	1	160000	10	20061	20061	20052	20052	20061
160024	20060	150	0	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	5	20032	20060	20051	3	22	80010	20	80000	20	160000	20051	20213	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	11	5	2	8	25	2	1	1	9	6	20048	0	40	2	160000	10	20061	20061	20061	20061	20052
160024	20060	150	0	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	0	1	5	20032	20051	20060	3	22	80010	20	80000	20	160000	20060	20190	1	1	160021	10	9	10	10	160000	10	0	0	0	10036	8	5	1	5	34	2	2	2	8	8	20057	0	40	2	160000	10	20052	20052	20061	20061	20061
160024	20051	151	0	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20205	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	4	1	11	25	2	1	1	9	8	20048	0	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	156	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20199	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	5	1	13	25	2	1	1	7	7	20048	0	20	1	160000	10	20052	20061	20052	20052	20052
160024	20051	150	0	0	0	0	0	51	27	80010	10	80000	10	80000	50	640000	0	1	5	20041	20051	20051	3	22	80010	20	80000	20	160000	20051	20220	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	8	5	1	6	25	2	1	1	12	8	20048	0	20	2	160000	10	20052	20061	20061	20061	20052
160024	20051	151	0	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20199	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	5	1	7	25	2	1	1	7	8	20048	0	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	1	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20203	1	1	160021	10	9	10	10	160000	10	0	0	4	10029	8	5	1	15	25	4	1	1	6	5	20048	0	40	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	0	239	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20217	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	8	5	1	5	25	2	1	1	8	5	20048	0	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	151	0	0	0	0	0	445	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20194	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	5	1	13	25	2	1	1	11	7	20048	0	20	1	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  ssra v0.2s, v16.2s, #3
  ssra v1.2s, v16.2s, #3
  ssra v2.2s, v16.2s, #3
  ssra v3.2s, v16.2s, #3
  ssra v4.2s, v16.2s, #3
  ssra v5.2s, v16.2s, #3
  ssra v6.2s, v16.2s, #3
  ssra v7.2s, v16.2s, #3
  ssra v8.2s, v16.2s, #3
  ssra v9.2s, v16.2s, #3
  ssra v10.2s, v16.2s, #3
  ssra v11.2s, v16.2s, #3
  ssra v12.2s, v16.2s, #3
  ssra v13.2s, v16.2s, #3
  ssra v14.2s, v16.2s, #3
  ssra v15.2s, v16.2s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40923	304	3	1	1	1	16	11	1200	1584	2922	345	161173	102	161561	102	161125	505	1292972	1	40714	40821	40874	20101	84	20343	161935	204	161646	206	323504	40923	40866	19	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	1	0	1	0	12	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	118	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	97	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	4	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	299	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	47	0	3	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40112	40049	40158
160204	40154	300	0	0	0	1	0	0	12	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	4	0	0	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	49	0	3	0	1	1	1	10120	2	24	2	2	40045	160000	100	40049	40049	40049	40049	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	11	8	40036	20	6	160000	10	40040	40040	40103	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	10022	3	1	1	8	16	2	1	1	8	9	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40099	300	1	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	1106	0	10022	3	1	1	6	16	2	1	1	5	10	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	5	12	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	8	16	40476	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	11	160000	50	1280000	1	1	40020	40039	40039	20005	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10079	3	1	1	5	16	2	1	1	5	8	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	9	16	2	1	1	14	10	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	10	16	2	1	1	8	8	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	88	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	9	16	2	1	1	14	9	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	9	16	2	1	1	6	13	40036	20	6	160000	10	40040	40040	40040	40040	40040

SSRA (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations