Firestorm: SSRA (vector, 4S) measurements

Code:

  ssra v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	3	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	42	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	39	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	10	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  ssra v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	348	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	12	124	29539	25	10100	100	10000	100	10000	500	4277313	30018	0	30085	30037	28265	8	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	631	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	16	1	1	29634	0	10000	100	30086	30085	30038	30038	30038
10204	30037	225	0	0	534	241	29548	44	10100	100	10000	119	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	12	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	557	29548	25	10100	100	10000	100	10000	500	4277313	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	296	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	339	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	300	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	1156	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	900	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	5	0	0	0	640	2	16	2	2	29630	2	10000	10	30038	30038	30038	30228	30085
10024	30037	225	0	0	0	0	0	531	0	103	29548	25	10010	10	10000	10	10298	50	4277313	1	30162	0	30037	30037	28292	3	28838	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	1487	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	33	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	384	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	955	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  ssra v0.4s, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	9	0	0	747	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	3	7	936	616	0	4595	29493	158	10177	126	10056	120	11050	626	4287086	1	30306	30375	30420	28274	42	28863	11171	226	11168	222	22654	30371	30371	8	1	10201	100	99	100	100	10000	100	2	3	0	0	22095	0	1	1	1	739	0	40	0	0	29645	10	10000	100	30467	30422	30456	30422	30371
10204	30404	228	1	0	9	10	1188	880	0	6537	29456	213	10203	127	10080	130	11450	642	4290166	0	30378	30506	30512	28321	51	28913	11478	228	11669	232	24668	30561	30514	12	1	10201	100	99	100	100	10000	100	0	0	0	4	27805	0	1	1	1	976	3	97	2	3	29829	8	10000	100	30646	30457	30325	30373	30470
10204	30368	237	1	1	6	11	1584	792	1	4721	29427	155	10175	136	10088	130	11350	658	4287976	0	30310	30322	30418	28290	50	28855	11941	248	12322	244	22646	30376	30227	15	1	10201	100	99	100	100	10000	100	0	2	0	2	36215	2	1	1	1	1011	5	120	3	3	30062	16	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	1	5912	29547	25	10100	100	10000	100	10000	632	4278512	1	30018	30037	30037	28252	6	28749	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	1	0	3	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30054	30037	30037	28252	15	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	24	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	884	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30085	30038
10024	30037	225	0	468	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	378	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	336	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	400	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	377	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10025	30037	224	0	423	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	660	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	635	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ssra v0.4s, v8.4s, #3
  movi v1.16b, 0
  ssra v1.4s, v8.4s, #3
  movi v2.16b, 0
  ssra v2.4s, v8.4s, #3
  movi v3.16b, 0
  ssra v3.4s, v8.4s, #3
  movi v4.16b, 0
  ssra v4.4s, v8.4s, #3
  movi v5.16b, 0
  ssra v5.4s, v8.4s, #3
  movi v6.16b, 0
  ssra v6.4s, v8.4s, #3
  movi v7.16b, 0
  ssra v7.4s, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	da	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160205	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20111	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20169	20066	20159	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	20066	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10031	13	5	1	13	20	2	1	1	7	11	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10036	3	5	1	12	20	2	1	1	12	14	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10035	13	5	1	8	20	2	1	1	8	11	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80430	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10038	13	5	1	12	20	2	1	1	8	13	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10035	13	5	1	8	20	2	1	1	8	11	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10039	13	5	1	13	20	2	1	1	8	14	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10034	13	6	1	8	20	2	1	1	13	7	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10031	13	5	1	12	20	2	1	1	7	11	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	516	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10031	13	5	2	14	20	2	1	2	8	11	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20050	150	0	729	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10035	13	6	1	13	20	2	1	1	8	11	20043	15	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  ssra v0.4s, v16.4s, #3
  ssra v1.4s, v16.4s, #3
  ssra v2.4s, v16.4s, #3
  ssra v3.4s, v16.4s, #3
  ssra v4.4s, v16.4s, #3
  ssra v5.4s, v16.4s, #3
  ssra v6.4s, v16.4s, #3
  ssra v7.4s, v16.4s, #3
  ssra v8.4s, v16.4s, #3
  ssra v9.4s, v16.4s, #3
  ssra v10.4s, v16.4s, #3
  ssra v11.4s, v16.4s, #3
  ssra v12.4s, v16.4s, #3
  ssra v13.4s, v16.4s, #3
  ssra v14.4s, v16.4s, #3
  ssra v15.4s, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	1	0	0	648	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40250	19977	6	19990	160120	200	160032	200	320064	40039	40244	1	1	160201	100	99	100	100	160000	100	0	0	5	0	0	0	1	1	1	10118	2	16	2	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	18	0	505	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	2	16	1	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	6	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10193	1	16	2	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	2	40036	160000	100	40040	40146	40248	40263	40040
160204	40088	300	1	0	0	0	42	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	2	16	2	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	2	16	1	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	45	0	51	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160140	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	0	1881	0	1	1	1	10118	1	16	2	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	5	2	0	0	1	1	1	10118	2	16	2	2	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160312	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	2	16	2	1	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	300	0	0	0	0	15	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	2	10022	3	1	1	21	16	1	1	1	18	16	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	30	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	15	16	2	1	1	14	14	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	24	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	18	16	1	1	1	16	18	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	12	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	13	19	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	438	90	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	17	16	2	1	1	12	17	40036	0	16	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	45	67	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160422	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	18	16	2	1	1	17	19	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	45	17184	338	161670	10	161959	10	161779	50	1294772	1	1	0	40978	40915	41215	20133	0	96	20604	161995	20	162398	20	324632	41166	40915	18	1	160021	10	9	10	10	160000	10	4	0	0	1	0	2	10220	6	2	2	24	158	4	2	2	31	20	40506	0	30	10	160000	10	40776	40693	40659	40755	40604
160024	40649	316	6	1	0	1	426	3961	482	160207	10	160000	10	161371	50	1289088	1	1	0	40773	40904	41005	20132	0	33	20204	160854	20	160000	20	321674	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	55	30	0	10022	3	1	1	17	16	2	1	1	17	16	40036	0	20	7	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	45	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40044	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	17	16	2	1	1	13	18	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	66	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	6	1	2	17	16	4	1	1	16	16	40036	0	40	12	160000	10	40040	40040	40040	40040	40040

SSRA (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations