Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBL2 (vector, 4S)

Test 1: uops

Code:

  ssubl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715082168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000371011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000276196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000010071011611197910100001002003820038200382003820038
10204200371500000084196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611966510010100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000726196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150082196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500657196872510010101000010100005028476800200182003720037184443187671001020101632020324200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500677196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000664216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500679196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500251196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715012611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000527284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715001251968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715001491968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715001681968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubl2 v0.4s, v8.8h, v9.8h
  ssubl2 v1.4s, v8.8h, v9.8h
  ssubl2 v2.4s, v8.8h, v9.8h
  ssubl2 v3.4s, v8.8h, v9.8h
  ssubl2 v4.4s, v8.8h, v9.8h
  ssubl2 v5.4s, v8.8h, v9.8h
  ssubl2 v6.4s, v8.8h, v9.8h
  ssubl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200671500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815005572580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815092304480208100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002009020039200392003920039
80204200381500402580100100800001008000050064000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000502003116112003580000102003920039200392003920039
80024200381500602580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502053116112003580000102003920039200392003920039
800242003815004272580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502054116112003580000102003920039200392008820039
800242003815094192580010108000013800005064000015200192009520088999631001880010208000020160000200382003811800211091010800001010502054116112003580000102003920039200392003920039
800242003815003925800101080000108000050640000152001920038201471000431001880010208009620160000200382003811800211091010800001002502054116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001010502054116112003580000102003920039200392003920039
80024200381509602580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502054116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502054116112003580000102003920039200392003920039
800242003815012392580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502054116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000502054116112003580000102003920039200392008720039