Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBL (vector, 2D)

Test 1: uops

Code:

  ssubl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
100420371596611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
100420371512611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
100420371596611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubl v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715001281968725101001001000010010000500284768020054200372003718422318745101002001000020020000200372003711102011009910010010000100007102161119791100001002003820038200382003820038
102042003715021611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715033611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715018611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
10204200371506611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715021611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371491000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000030611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201017220200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000150611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010830202165820320202736110021109101010000102220001204007584563319970210000102027620321203102032320180
10024203221520104667252825271962113410076161007216103046528553781202342032020085184662818878109732011007222200220319203237110021109101010000100000121121307223492219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubl v0.2d, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001008707101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718436318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100317101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001008107101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001008407101161119791100001002003820038200382003820038
1020420037150246119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
100242003715000001206119687251001010100001010000502847680020018200372024018444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820085200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102008620038200382003820086
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200372110021109101010000100001000640216221978510000102003820038200382003820038
1002420037149000012010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100001000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640224221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318790100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubl v0.2d, v8.2s, v9.2s
  ssubl v1.2d, v8.2s, v9.2s
  ssubl v2.2d, v8.2s, v9.2s
  ssubl v3.2d, v8.2s, v9.2s
  ssubl v4.2d, v8.2s, v9.2s
  ssubl v5.2d, v8.2s, v9.2s
  ssubl v6.2d, v8.2s, v9.2s
  ssubl v7.2d, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150000009004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000000511021611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000010000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000040000511011611200350800001002003920039200392003920039
8020420038150000000004025804961008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000600511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000070000511011611200350800001002003920039200392003920039
80204200381500000000020825801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000000004025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000000023025801001008000010080000500640000200192003820038997303999680100200800002001600002003820038118020110099100100800001000010000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502013161162003580000102003920039200392003920039
800242003815001022580010108000010800005064000002001920038200899996310018801112080000201601942013820038318002110910108000010063050204165112003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000103905020516652003580000102003920039200392003920039
800242003815003925800101080000108000050640772020019200382003899963100188001020800002016000020038200381180021109101080000100005020616552003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020916642003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100605020616672003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050201016542003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010010205020716542003580000102003920039200392003920039
800242003815003925800101080000108000050642300020019200382003899963100188001020800002016000020038200381180021109101080000100005020716552003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010057050205165112003580000102003920039200392003920039