Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBL (vector, 4S)

Test 1: uops

Code:

  ssubl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371551082168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371512061168725100010001000264680020182037203715723189510001000200020372037111001100020073116111787100020382038203820382038
10042037150061168725100010001000264680020182037207315723189510001000200020372037211001100000073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723190710001000200020372037111001100000090116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371512061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100001073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000001206119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611198270100001002003820038200382003820038
102042003715000001208219687251010010010000118100005002848963020054200372003718422318745101002041000020020332201782003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003721102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000003071011611197910100001002003820038200382003820038
102042003715000000038819687251010010010000100100005002847680020018200372003718422318745101002001000020020334200862003711102011009910010010000100200000071011611197910100001002003820087200382008520038
1020420037150010013206119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000100071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020662200372003711102011009910010010000100000003071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500189196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616551978510000102003820038200382003820038
10024200371501261196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001030640516671978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003731100211091010100001000640516551978510000102003820038200382003820038
10024200371500441196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616651978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616561978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640516661978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616651978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003731100211091010100001000661516561978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001046640516551978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640516451978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubl v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037149006119687251010010010000100100005002847680020018200372003718422318745101002001000020020662200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150108219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010012100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500010619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
100242003715000156196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100122010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500082196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000640316331982310000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubl v0.4s, v8.4h, v9.4h
  ssubl v1.4s, v8.4h, v9.4h
  ssubl v2.4s, v8.4h, v9.4h
  ssubl v3.4s, v8.4h, v9.4h
  ssubl v4.4s, v8.4h, v9.4h
  ssubl v5.4s, v8.4h, v9.4h
  ssubl v6.4s, v8.4h, v9.4h
  ssubl v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021611200350800001002003920039200392003920039
802042003815000090028025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000000402580100100800001008000050064000012001920038200389973399968010020080096202160194200882009221802011009910010080000100272125100511011611200350800001002003920039201122003920039
8020420038150011180120021549802071248009210080099522640776020072200882008999837100238021220080097200160194201362010031802011009910010080000100023104604511011611200350800001002008920109200902010020149
8020420101150110156212126250802011138009410080097500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000015004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000020182200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200891500000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011621200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200840800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150030392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011165112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020101610112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020111610132003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020101610102003580000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011167112003580000102003920039200392003920039
8002420038150008125800101080000108000050640000120019200382003899963100188001020800002016000020038200871180021109101080000100005020121611112008480000102009020098200392003920039
80024200381511039258001010800001080000506400001200192003820139100053100188001020800002016000020038200381180021109101080000100005039123311102003580000102003920039200392003920039
800242003815000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502014161072003580000102003920039200392003920039
80024200381500051425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020121612122003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100035020101611132003580000102003920039200392003920039