Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBL (vector, 8H)

Test 1: uops

Code:

  ssubl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037156116872510001000100026468010201820372037157231895100010002000203720371110011000007300316221787100020382038203820382038
10042037166116872510001000100026468000201820372037157231895100010002000203720371110011000007350216221787100020382038203820382038
10042037166116872510001000100026468005201820372037157231895100010002000203720371110011000007300216221787100020382038203820382038
10042037156116872510001000100026468010201820372037157231895100010002000203720371110011000007300216221787100020382038203820382038
10042037156116872510001000100026468015201820372037157231895100010002000203720371110011000007350216221787100020382038203820382038
10042037166116872510001000100026468015201820372037157231895100010002000203720371110011000007300216221787100020382038203820382038
10042037156116872510001000100026468015201820372037157231895100010002000203720371110011000067350216221787100020382038203820382038
10042037156116872510001000100026468015201820372037157231895100010002000203720371110011000007350216221787100020382038203820382038
10042037166116872510001000100026468015201820372037157231895100010002000203720371110011000607300216221787100020382038203820382038
10042037156116872510001000100026468015201820372037157231895100010002000203720371110011000016187351216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000009971001161119791100001002003820038200382003820038
1020420037150000103196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100200071001161119791100001002003820038200382003820038
1020420037150000726196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100004071001161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100001374011161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071001161119891100001002003820038200382003820038
102042003715010061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000001871001161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000013271001161119791100001002003820038200382003820038
102042003715000061196872510100100100001041000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100002906402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100010006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000053619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000306402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371660000000191319687251001010100001010000612847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500000014919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002848050020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000010319687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000010071011611197910100001002003820038200382003820038
10204200371500000008419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371490000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371550000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640416431978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640416341978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000102100640416441978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316441978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316441978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640416441978510000102003820038200382003820038
10024200371610081119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640416341978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100100640316341978510000102003820038200382003820038
100242003715001086119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316441978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640416341978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubl v0.8h, v8.8b, v9.8b
  ssubl v1.8h, v8.8b, v9.8b
  ssubl v2.8h, v8.8b, v9.8b
  ssubl v3.8h, v8.8b, v9.8b
  ssubl v4.8h, v8.8b, v9.8b
  ssubl v5.8h, v8.8b, v9.8b
  ssubl v6.8h, v8.8b, v9.8b
  ssubl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000000000124258010010080000100800005006400001020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110021611200350800001002003920039200392003920039
802042003815000000109040258010010080000100800005006400000020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110011611200350800001002003920039200392003920039
802042003815000000000039258010010080000100800006266400001020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110011611200350800001002003920039200392003920039
8020420038150000000000822580100100800001198000050064000000200192003820038997339996802372008000020016000020038200381180201100990100100800001000000102105110051611200350800001002003920039200392003920039
8020420038149000000000738258010010080000100800005006400001020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110011611200350800001002003920039200392003920039
8020420038150000010060402580100100800001008000050064000000200192003820038997339996801002048078120216000020038200381180201100990100100800001000000000051290116312003519800001002003920039200392003920039
802042003815000000000040258010010080000100800005006400000020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110011611200350800001002003920039200392003920039
802042003815000000000040258010010080000100800005006400000020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005112011611200350800001002003920039200392003920039
802042003815000000000040258010010080000100800005006400001020019200382003899733999680125200800002001600002003820038118020110099010010080000100000000005110011631200350800001002003920039200392003920039
802042003815000000000040258010010080000100800005006400001020019200382003899733999680100200800002001600002003820038118020110099010010080000100000000005110011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715000016925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020416442003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020316942003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416642003580000102003920039200392003920039
80024200381500603925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020616762003580000102003920039200392003920039
800242003814900060925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020616782003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020316542003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100035020316762011880000102003920039200392003920039
80024200381501132104387325800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100305020416672003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020316682003580000102003920039200392003920039
80024200381500006225800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416642003580000102003920039200392003920039