Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBW2 (vector, 2D)

Test 1: uops

Code:

  ssubw2 v0.2d, v0.2d, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371691561687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715198611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715126611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371584611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371551611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371501561687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubw2 v0.2d, v0.2d, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500003750611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000120611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020181200371110201100991001001000010000010071011611197910100001002003820038200382003820038
1020420037150010720611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284896312001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042013515000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002112000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200101672002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000020200671011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010169202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500014719687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500126119687251001010100001310000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010331222000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
100242003715002976119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200373110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
100242003715003276119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubw2 v0.2d, v1.2d, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371502484196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007341161119791100001002003820038200382003820038
102042003715024361196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715072156196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500427196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2c3branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000100006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000060711968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000060611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000090611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820085200382003820038
1002420037150011159885371968725100101010000101000050284896312001820037200371844471878510165201016320203362008420084211002110910101000010000000006612243319824210000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubw2 v0.2d, v8.2d, v9.4s
  ssubw2 v1.2d, v8.2d, v9.4s
  ssubw2 v2.2d, v8.2d, v9.4s
  ssubw2 v3.2d, v8.2d, v9.4s
  ssubw2 v4.2d, v8.2d, v9.4s
  ssubw2 v5.2d, v8.2d, v9.4s
  ssubw2 v6.2d, v8.2d, v9.4s
  ssubw2 v7.2d, v8.2d, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000013504025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511051622200350800001002003920039201102003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
802042003815000003004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038100053999680100200800002001600002003820038118020110099100100800001000000000511033823200350800001002003920039200392003920039
802042003815000004804025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381500000304025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021622200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815012392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001030502000816532003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502000516352003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502000516642003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502000516552003580000102003920039200392003920039
800242003815018392580010108000010800005064000000200192003820038999631012880010208000020160000200382003811800211091010800001000502000316532003580000102003920039200392011320039
8002420038150420392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000502000316452003580000102003920039200392003920039
800242003815062292580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502000516532003580000102003920039200392003920039
80024200381500392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000502000516552003580000102003920039200392003920039
800242003815015392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000502000516532003580000102003920039200392003920039
8002420038150300392580010108000010800005064000010200192003820038999631009880010208000020160000200382003811800211091010800001000502000416352003580000102003920039200392003920039