Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSUBW2 (vector, 4S)

Test 1: uops

Code:

  ssubw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0309181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073316331787100020382038203820382038
100420371500061168725100010001000264680120182037203715723189510001000200020372037111001100000073316331787100020382038203820382038
100420371500061168725100010001000264680120182037203715723189510001000200020372037111001100001073316331787100020382038203820382038
1004203716000611687251000100010002646800201820372037157231895100010002000203720371110011000012073316331787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100004073316331787100020382038203820382038
1004203716000141168725100010001000265963020182037203715723189510001000200020372037111001100001073316331787100020382038203820382038
10042037150001041687251000100010002646801201820372084157231906115210002000203720371110011000017073316331787100020382038203820382085
100420371600061168725100010001000264680020182037203715723189510001000200020372037111001100000073316331787100020382038203820382038
10042037151001051687251000100010002646800201820372037157231895100010002000203720371110011000018273316331787100020382038203820382038
1004203715000165168725101210001000264680020542037203715723189510001000200020372037111001100003073316331787100020382038203820382038

Test 2: Latency 1->2

Code:

  ssubw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000008219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100019071011611197910100001002008620038200382003820038
102042003715000000014519687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000012071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200842003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000016019687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100009071011611197910100001002008520038200382003820038
10204200371500000006119687251010010010000100100005882847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100003071011611197910100001002003820038200382003820038
1020420037150010010406119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820087200862008620038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000002511968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006403162219785010000102003820038200382003820038
1002420037150000000001241968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000020006402162219785010000102003820038200382003820038
1002420037150000001500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000004200821968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000005361968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000010306402162219785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000306402162219785010000102003820038200382003820038
1002420037150000000001451968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000000611968725100101010000101000061284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000005501968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ssubw2 v0.4s, v1.4s, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000000082196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
10204200371500000000084196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000004000071011611197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
102042003715000000000126196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000001000071011611197910100001002003820038200382003820038
10204200371490000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000001030071011611197910100001002003820038200382003820038
102042003715000000000835196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000001000071011611197910100001002003820038200382003820038
102042003715000000000166196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
102042003715000000000166196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000003000171011611197910100001002003820038200382003820038
102042003715000000000151196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500153196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500168196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640116221978510000102003820038200382003820038
1002420037150084196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200862003820038
10024200371490631196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010111000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
10024200371500331196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150084196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ssubw2 v0.4s, v8.4s, v9.8h
  ssubw2 v1.4s, v8.4s, v9.8h
  ssubw2 v2.4s, v8.4s, v9.8h
  ssubw2 v3.4s, v8.4s, v9.8h
  ssubw2 v4.4s, v8.4s, v9.8h
  ssubw2 v5.4s, v8.4s, v9.8h
  ssubw2 v6.4s, v8.4s, v9.8h
  ssubw2 v7.4s, v8.4s, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051104161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100151101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038149040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120073800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000000002952580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202163220035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162320035080000102003920039200392003920039
800242003815000000001442580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162220035080000102003920039200392003920039
8002420038150000001710392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100010050202162220035080000102003920039200392003920039
80024200381500000000832580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100030050203162220035080000102003920039200392003920039
80024200381501110001048145800101180000108000060640768200662008620112100046100468001020800962016000020094200942180021109101080000100200187351062604320035380000102027420290202412028420291
80024202351510004567235278682802001480281118029261643040201732029320190100271810018804022080389201609782024020288618002110910108000010201446850877583320233380000102028920290202932023720141
800242024115201155546264812580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162220035080000102003920039200392003920039
8002420038150000000010992580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162320035080000102003920039200392003920039
800242003815000000601922580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162220035080000102003920039200392003920039