Firestorm: ST1 (multiple, 1 reg, 16B) measurements

Code:

  st1 { v0.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29136	234	4	1	5	1	6	1	0	0	132	2	0	0	4663	28518	2	0	23899	1000	1000	1000	5000	24	0	0	15943	28271	28984	3	28	1000	1001	2000	28904	28989	1	1	61001	1000	1000	1001	1	2	1	1001	0	0	1	1000	1	2	1	0	12936	9238	6903	3138	0	42	21404	3322	3800	15	43	45	4	28335	15789	12857	15384	1000	29020	28974	28959	28939	28987
61004	28891	233	0	1	2	1	0	1	1	0	0	90	0	0	4644	28511	0	0	24142	1000	1000	1001	5005	22	1	8	15905	28153	28743	3	10	1000	1000	2000	28634	28564	1	1	61001	1000	1000	1002	1	4	0	1001	0	1	1	1000	1	0	1	1	13246	9371	6866	3136	1	44	21193	3220	3803	7	37	43	2	28155	15818	13092	15250	1000	28780	28820	28733	28720	28677
61004	28725	231	0	1	4	2	4	0	0	0	0	1	0	0	4787	28420	1	2	23902	1000	1000	1000	5000	20	0	0	15925	28167	28770	3	10	1000	1000	2000	28727	28671	2	1	61001	1000	1000	1005	1	3	3	1001	1	0	1	1000	1	4	1	2	13243	9430	6916	3153	0	46	21259	3163	3803	14	37	39	4	28310	15552	13177	15036	1000	28849	28822	28906	28808	28797
61004	28865	232	0	1	2	2	4	0	0	0	0	1	0	0	4670	28449	0	2	23838	1000	1000	1000	5000	19	0	0	15898	28116	28794	3	10	1001	1000	2000	28846	28658	1	1	61001	1000	1000	1003	1	2	1	1001	0	1	1	1000	1	0	1	1	13013	9352	6880	3228	0	46	21108	3207	3801	14	48	44	3	28164	15705	13084	15132	1000	28865	28901	28883	28814	28723
61004	28749	231	0	1	3	1	1	1	1	0	0	2	0	0	4656	28443	1	1	23775	1000	1000	1000	5000	29	0	0	15953	28043	28843	3	10	1000	1000	2000	28684	28708	1	1	61001	1000	1000	1001	1	4	2	1001	0	1	1	1000	1	4	1	0	13152	9291	6906	3168	0	39	21217	3248	3805	15	44	41	3	28184	15579	12917	15022	1000	28781	28881	28867	28874	28759
61004	28820	231	0	1	3	1	3	0	0	0	0	2	0	0	4729	28474	2	2	23808	1000	1000	1000	5000	24	0	8	15941	28209	28876	3	10	1000	1000	2000	28755	28848	1	1	61001	1000	1000	1002	1	4	0	1001	0	1	1	1000	1	0	1	0	12951	9270	6871	3149	1	45	21303	3202	3803	14	46	48	4	28225	15538	13117	15189	1000	28967	28846	28918	28858	28768
61004	28841	231	0	1	3	1	2	1	0	0	0	89	0	0	4704	28352	0	0	23806	1000	1000	1000	5000	17	0	8	15926	28202	28905	3	10	1000	1000	2000	28741	28678	1	1	61001	1000	1000	1001	4	4	0	1001	0	2	1	1000	1	0	1	1	13085	9586	6970	3111	2	41	21084	3235	3807	19	46	48	3	28209	15721	13299	15056	1000	28812	28765	28735	28784	28851
61004	28863	232	0	1	0	2	2	1	0	0	0	1	0	0	4703	28542	0	2	24235	1000	1000	1000	5000	17	0	8	15931	28236	29046	3	10	1000	1000	2000	28746	28877	1	1	61001	1000	1000	1003	2	4	0	1001	1	1	1	1000	1	0	1	1	13075	9190	6888	3139	1	39	21221	3266	3800	18	40	42	3	28320	15568	13175	14930	1000	28741	28561	28703	28764	28683
61004	28623	230	0	1	3	1	4	1	0	0	135	1	0	0	4602	28509	0	0	23703	1000	1000	1000	5000	18	0	0	15946	28052	28832	3	10	1000	1000	2000	28692	28739	1	1	61001	1000	1000	1002	1	0	1	1001	0	1	1	1000	1	2	1	0	13245	9507	6879	3080	0	43	21577	3212	3804	15	42	45	2	28063	15541	13124	15193	1000	28758	28827	28929	28661	28637
61004	28792	231	0	1	2	0	2	1	0	0	0	2	0	0	4724	28365	2	2	23849	1000	1000	1000	5000	19	0	0	15958	28027	28602	3	10	1000	1000	2000	28789	28694	1	1	61001	1000	1000	1002	3	0	1	1001	0	0	1	1000	1	0	1	0	13182	9292	6956	3214	1	41	20993	3326	3803	12	42	39	3	28084	15915	13247	15510	1000	28904	28668	28803	28751	28660

Count: 8

Code:

  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]
  st1 { v0.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	322	0	0	0	0	0	0	0	0	3	0	0	40029	16	16	0	25	80100	100	80000	100	80000	500	1839472	0	40017	41563	42259	29955	3	30000	80100	200	80000	200	160238	40435	40436	2	1	80201	100	99	100	100	80000	80000	100	80000	0	44	0	80002	2	0	8	80002	2	42	0	5110	14	16	15	16	40413	80000	100	40043	40044	40043	40043	40044
80204	40042	311	0	0	0	0	0	0	0	18	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	40017	40043	40043	29956	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80000	0	0	2	80002	2	42	0	5110	13	16	13	13	40040	80000	100	40043	40044	40041	40044	40043
80204	40043	310	0	0	0	0	0	0	0	0	3	0	0	40028	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	40018	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	5	80002	2	0	0	5110	6	16	12	8	40039	80000	100	40044	40041	40044	40043	40055
80204	40040	310	0	0	0	0	0	0	0	12	3	0	0	40028	0	16	1	25	80100	100	80000	100	80000	500	1840000	0	40017	40042	40043	29956	3	30000	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	0	0	80002	2	42	0	5110	13	16	13	25	41467	80000	100	40043	40044	40043	40044	40043
80204	40043	321	0	0	0	0	0	0	0	12	0	0	0	40030	16	16	0	25	80100	100	80060	100	80108	500	1840028	0	40017	40043	40043	29955	3	30012	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	2	80002	2	42	0	5110	13	16	13	13	40039	80000	100	40044	40043	40041	40043	40043
80204	40043	322	0	0	0	0	0	0	0	3	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	40017	40043	40042	29953	3	30000	80100	200	80000	200	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	0	80002	2	42	0	5110	13	16	13	10	40039	80000	100	40043	40043	40041	40044	40043
80204	40042	310	0	0	0	0	0	0	0	12	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	40017	40043	40042	29956	3	30012	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	31	80002	0	0	0	80000	2	0	0	5110	13	16	11	14	40039	80000	100	40043	40044	40043	40044	40044
80204	40043	310	0	0	0	0	0	0	0	12	0	0	1	40027	0	16	1	25	80100	100	80000	100	80000	511	1839448	0	40029	40054	40054	29955	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	1	0	3	80002	2	42	0	5110	13	16	12	7	40039	80000	100	40043	40043	40043	40044	40044
80204	40042	310	0	0	0	0	0	0	0	12	3	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839496	0	40015	40042	40042	29956	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	28	80002	0	0	23	80002	2	42	0	5110	15	16	12	13	40040	80000	100	40043	40041	40043	40041	40043
80204	40042	311	0	0	0	0	0	0	0	12	0	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	40017	40042	40040	29955	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	1	0	8	80002	2	42	0	5110	15	16	10	14	40040	80000	100	40043	40041	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4c	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	310	0	0	0	6	3	0	0	1	40584	16	16	0	1	25	80070	10	80000	10	80216	50	1856581	0	40017	40044	40042	29977	3	30022	80010	20	80000	20	160278	40042	40042	2	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	1	0	2	80002	2	34	0	0	5020	33	16	0	32	32	40039	80000	10	40043	40043	40043	40041	40043
80024	40049	321	0	0	0	18	3	0	0	0	40035	16	0	0	0	25	80010	10	80000	10	80000	50	1839424	0	40015	40042	40042	29977	3	30029	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	1	0	8	80002	2	38	0	0	5020	13	16	0	32	12	40039	80000	10	40052	40051	40052	40051	40183
80024	40040	321	0	0	0	12	9	0	0	0	40025	16	16	0	0	25	80010	10	80000	10	80000	50	1844245	0	40017	40049	40042	29977	3	30030	80118	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	1	0	14	80002	2	34	0	0	5020	32	16	0	33	33	40048	80000	10	40043	40043	40043	40043	40043
80024	40042	331	0	0	0	0	7	0	0	0	40166	0	16	0	0	25	80070	10	80000	10	80000	50	1839448	0	40015	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	80000	1	0	2	80062	2	42	0	0	5020	37	16	0	36	36	40040	80000	10	40041	40182	40184	40055	40043
80024	40042	331	0	0	0	141	0	0	0	0	40027	16	0	0	0	55	80010	10	80000	10	80000	50	1839448	0	40017	40045	40043	29977	3	30023	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	80002	3	239	2	80002	2	42	0	0	5039	33	16	0	33	33	40039	80000	10	40601	42219	42255	42116	40044
80024	40042	321	0	1	0	12	91	0	0	0	40027	16	16	0	1	25	80010	10	80000	10	80000	50	1839448	1	40017	40042	40042	29977	3	30028	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	10	80000	80000	10	80060	0	34	80002	0	0	5	80062	2	34	2	0	5020	33	16	0	33	15	40056	80000	10	40051	40052	40051	40052	40043
80024	40042	328	0	1	0	0	94	0	0	1	40034	16	16	0	0	55	80010	10	80000	10	80000	50	1839424	0	40015	40042	40042	29977	3	30022	80010	20	80000	20	160000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	1	0	2	80002	2	34	0	0	5020	33	16	0	33	33	40048	80000	10	40043	40043	40043	40043	40051
80024	40042	322	0	0	0	21	6	0	0	1	40034	16	16	0	0	55	80010	10	80000	10	80000	50	1839424	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	160242	40051	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80062	1	0	5	80000	2	34	0	0	5020	33	16	504	15	32	40040	80000	10	40060	40043	40043	40043	40180
80024	40051	321	1	0	0	12	91	0	0	0	40027	16	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	40022	40042	40051	29977	3	30029	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80060	0	34	80002	1	0	1608	80000	2	34	0	0	5020	35	16	0	35	23	40050	80000	10	40043	40043	40043	40043	40052
80024	40181	322	0	15	12	132	3	0	0	0	40027	16	16	0	0	25	80010	10	80360	10	80972	50	1894939	0	40017	40050	40042	29977	3	30022	80118	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	1	0	2	80002	2	34	0	0	5020	32	16	0	32	21	40039	80000	10	40050	40041	40060	40050	40183

ST1 (multiple, 1 reg, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations