Firestorm: ST1 (multiple, 1 reg, 1D) measurements

Code:

  st1 { v0.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	28877	232	3	1	4	0	0	1	0	0	0	0	1	0	4638	28411	1	1	23835	1000	1000	1000	5000	12	15948	28115	28835	3	10	1000	1000	2000	28676	28606	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	3	0	0	13093	9296	6891	3109	1	62	21246	3178	3810	25	68	66	28215	15765	13180	15031	1000	28860	28778	28822	29017	28834
61004	28774	231	0	0	1	0	0	3	0	0	0	132	0	1	4695	28476	1	1	23702	1000	1000	1000	5000	15	15934	28233	28739	3	10	1000	1000	2000	28757	28670	1	1	61001	1000	1000	1000	0	3	0	1001	0	0	0	1000	0	0	0	13166	9263	6856	3115	1	66	21212	3272	3814	22	68	68	28222	15355	12982	14973	1000	28833	28881	28825	28797	28811
61004	28868	232	0	0	2	0	0	1	0	0	0	0	0	0	4775	28511	1	0	23726	1000	1000	1000	5000	17	15926	28137	28863	3	10	1000	1000	2000	28634	28623	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	0	1000	3	0	0	13028	9425	6940	3178	0	62	21228	3232	3813	19	69	72	28200	15580	13178	14922	1000	28892	28741	28796	28884	28763
61004	28801	232	0	0	1	0	1	1	0	0	0	0	0	0	4770	28554	1	1	23871	1000	1000	1000	5000	14	15931	28026	28785	3	10	1000	1000	2000	28817	28765	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	3	0	0	13164	9294	6965	3121	0	69	21231	3198	3818	29	70	65	28287	15482	13027	14897	1000	28857	28895	28884	28858	29005
61004	28809	230	0	0	2	0	0	1	0	0	0	0	0	0	4698	28529	1	1	23776	1000	1000	1000	5000	12	15995	28117	28900	3	10	1000	1000	2000	28809	28793	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	0	0	13079	9314	6923	3079	0	69	21174	3181	3818	26	61	71	28343	15671	13216	15279	1000	28945	28924	28850	28910	28844
61004	28845	233	0	0	1	0	0	3	0	0	0	0	0	0	4649	28528	1	1	23953	1000	1000	1000	5000	12	15970	28190	28952	3	10	1000	1000	2000	28799	28723	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	3	0	0	13041	9243	6942	3198	0	67	21316	3198	3817	26	62	66	28233	15879	13082	15230	1000	28819	28772	28863	28733	28813
61004	28862	232	0	0	3	0	0	2	0	0	0	0	0	0	4769	28446	1	1	23851	1000	1000	1000	5000	17	15923	28266	28907	3	10	1000	1000	2000	28740	28806	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	0	0	13194	9151	6835	3110	3	67	21061	3147	3808	24	63	70	28184	15584	12767	14791	1000	28743	28770	28660	28718	28711
61004	28743	223	0	0	1	0	0	2	0	0	0	0	0	1	4664	28333	0	1	23703	1000	1000	1000	5000	17	15918	28058	28659	3	10	1000	1000	2000	28597	28672	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	3	0	0	13308	9558	6907	3172	1	72	21099	3123	3815	24	64	65	28129	15401	12839	15025	1000	28730	28709	28704	28624	28653
61004	28630	222	0	0	3	0	0	0	0	0	0	0	0	0	4722	28310	0	1	23692	1000	1000	1000	5000	17	15932	28000	28769	3	10	1000	1000	2000	28519	28625	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	0	0	13039	9606	6981	3194	1	64	21158	3152	3806	23	66	67	28171	15412	12999	14925	1000	28790	28667	28596	28626	28823
61004	28696	224	0	0	1	0	0	2	0	0	0	0	0	0	4637	28358	1	0	23668	1000	1000	1000	5000	18	15942	28087	28648	3	10	1000	1000	2000	28655	28487	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	0	1000	3	0	0	13268	9478	6999	3201	1	74	20958	3250	3810	29	66	63	28078	15481	13039	14989	1000	28641	28797	28668	28846	28692

Count: 8

Code:

  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]
  st1 { v0.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	310	0	0	0	0	3	1	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	40017	40043	40042	29956	3	30001	80100	200	80000	200	160000	40042	40043	2	1	80201	100	99	100	100	80000	80000	100	80062	42	28	80002	0	2	2067	80062	0	42	0	5110	3	16	1	1	40039	0	80000	100	40043	40043	40043	40043	40043
80204	40042	299	0	0	0	0	3	0	0	40025	0	0	1	25	80100	100	80000	100	80000	500	1839472	40018	40040	40122	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	0	2	80002	2	42	0	5110	1	16	1	1	40037	0	80000	100	40044	40043	40043	40043	40044
80204	40042	300	0	0	0	0	3	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40040	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	2	80002	2	42	0	5110	1	16	1	1	40040	0	80000	100	40043	40043	40044	40043	40055
80204	40042	300	0	0	0	0	3	0	0	40028	16	0	28	25	80100	100	80000	100	80000	500	1839472	40017	40043	40043	29955	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	0	80002	2	42	0	5110	1	16	1	1	40039	0	80000	100	40043	40044	40043	40043	40044
80204	40040	299	0	0	0	0	3	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	2	80182	2	42	0	5110	1	16	1	1	40039	0	80000	100	40043	40044	40043	40043	40041
80204	40040	300	0	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	40015	40054	40042	29956	3	30000	80100	200	80000	200	160000	40043	40042	1	1	80202	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	0	80002	2	42	0	5110	1	16	1	1	40039	0	80000	100	40043	40044	40043	40043	40041
80204	40043	300	0	0	0	0	3	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40042	29955	3	30000	80100	200	80000	200	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	0	80002	0	0	0	5110	1	16	1	1	40039	0	80000	100	40041	40055	40043	40041	40044
80204	40043	300	0	0	0	0	0	0	0	40025	16	16	1	25	80100	100	80000	100	80000	500	1839352	40017	40042	40042	29956	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	0	80000	0	0	0	5110	1	16	3	2	40039	0	80000	100	40043	40044	40041	40041	40044
80204	40043	300	0	0	0	0	0	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40042	29967	3	30000	80100	200	80000	200	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	2	80002	2	42	0	5110	1	16	1	1	40040	0	80000	100	40043	40044	40043	40043	40043
80204	40040	299	0	0	0	0	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	40017	40042	40054	29956	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	2	80002	2	42	0	5110	1	16	1	3	40040	0	80000	100	40044	40041	40043	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40054	311	12	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839472	0	40017	40040	40042	29975	3	30020	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	80002	0	8	80002	2	42	5020	4	16	8	3	5	40039	80000	10	40044	40044	40043	40043	40043
80024	40353	310	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40042	29978	3	30023	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	80002	0	2	80002	2	42	5020	5	16	0	5	5	40040	80000	10	40044	40043	40044	40043	40043
80024	40042	311	15	3	0	0	40025	16	16	0	25	80010	10	80000	10	80108	50	1848922	0	40018	40042	40042	29977	3	30022	80010	20	80000	20	160000	40053	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	5020	5	16	0	5	4	40039	80000	10	40360	40435	40435	40043	40434
80024	40042	324	0	607	0	0	40027	16	16	327	25	80010	10	80000	10	80000	50	1839424	0	40025	40042	40050	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	5020	5	16	0	3	5	40046	80000	10	40043	40041	40043	40049	40043
80024	40042	300	0	3	0	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1842142	0	40017	40042	40040	29984	3	30022	80010	20	80000	20	160000	40042	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	0	80000	2	34	5020	5	16	0	5	5	40039	80000	10	40043	40043	40041	40043	40043
80024	40040	300	12	3	0	0	40027	16	0	34	25	80010	10	80000	10	80000	50	1839352	0	40025	40042	40050	29985	3	30022	80010	20	80000	20	160000	40042	40050	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	5020	5	16	0	5	7	40039	80000	10	40043	40043	40043	40043	40041
80024	40040	299	0	9	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	8	80002	0	34	5020	4	16	0	5	5	40037	80000	10	40043	40043	40043	40043	40041
80024	40040	299	0	9	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40040	40040	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	0	5020	3	16	0	5	5	40039	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	9	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40042	40040	29977	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80000	0	5	80002	2	34	5020	7	16	0	4	4	40046	80000	10	40043	40051	40043	40043	40051
80024	40042	300	0	3	0	1	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40042	40040	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80002	0	2	80002	2	0	5020	5	16	0	4	5	40039	80000	10	40041	40043	40043	40041	40043

ST1 (multiple, 1 reg, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations