Firestorm: ST1 (multiple, 1 reg, 2D) measurements

Code:

  st1 { v0.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29342	226	2	0	5	0	0	6	0	0	0	0	1	0	0	4613	28787	0	0	24232	1000	1000	1000	5000	0	9	0	0	15955	28441	29372	3	10	1000	1000	2000	29167	29152	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	0	2	0	0	0	13030	9222	6907	3115	1	47	21702	3194	3808	21	51	47	28474	16162	13630	15962	1000	29251	29391	29339	29289	29267
61004	29464	227	0	0	6	0	0	6	0	0	0	270	1	1	0	4623	28887	0	0	24266	1000	1000	1000	5000	0	11	0	0	15966	28375	29377	3	10	1000	1000	2000	29272	29212	1	1	61001	1000	1000	1000	0	2	0	1000	1	0	0	1000	0	3	0	0	0	12981	9438	6919	3165	5	56	21669	3205	3818	13	54	51	28581	16245	13468	15808	1000	29149	29391	29335	29434	29351
61004	29419	227	0	0	9	0	0	4	0	0	0	51	0	0	0	4603	28730	1	0	24361	1000	1000	1000	5000	0	5	0	0	15961	28462	29305	3	10	1000	1000	2000	29152	29196	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	3	0	0	0	12942	9443	6943	3152	1	45	21710	3235	3813	10	52	51	28532	16136	13665	15221	1000	29304	29339	29298	29265	29479
61005	29285	227	0	0	4	0	0	6	0	0	0	54	0	1	0	4669	28783	0	0	24449	1000	1000	1000	5000	0	5	0	0	15961	28385	29311	3	10	1000	1000	2000	29229	29047	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	2	0	0	0	13073	9300	6909	3117	3	55	21619	3213	3820	12	56	59	28441	16075	13597	15220	1000	29316	29189	29312	29301	29376
61004	29386	227	0	0	7	0	0	6	0	0	0	48	0	0	0	4687	28800	0	0	24327	1000	1000	1000	5000	0	3	0	0	15959	28452	29355	3	10	1000	1000	2000	29237	29150	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	2	0	0	0	13040	9147	6892	3145	0	60	21730	3152	3815	12	51	53	28526	16360	13801	15856	1000	29265	29236	29324	29397	29280
61004	29320	227	0	0	6	0	0	7	1	0	0	36	1	0	0	4616	28856	0	1	24253	1000	1000	1000	5000	0	2	0	0	15962	28499	29351	3	10	1000	1000	2000	29254	29207	1	1	61001	1000	1000	1002	1	3	1	1001	0	1	1	1000	1	3	1	1	0	13131	9209	6917	3118	3	49	21620	3192	3812	11	47	51	28463	16442	13804	15570	1000	29425	29394	29353	29341	29299
61004	29351	227	0	1	7	1	0	6	1	0	0	321	1	0	0	4582	28717	0	0	24401	1000	1000	1000	5000	0	5	0	0	15964	28545	29374	3	10	1000	1000	2000	29190	29294	1	1	61001	1000	1000	1004	2	3	1	1001	0	1	1	1000	1	3	1	0	0	13104	9161	6890	3120	1	50	21672	3115	3821	11	50	50	28403	16467	13551	15410	1000	29368	29214	29162	29365	29264
61004	29396	227	0	0	8	0	0	4	0	0	0	3	0	0	0	4742	28860	1	1	24306	1000	1000	1000	5000	1	7	0	0	15970	28350	29396	3	10	1000	1000	2000	29117	29152	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	3	0	0	0	12960	9426	6879	3133	3	48	21612	3167	3813	12	48	53	28453	16186	13683	15673	1000	29414	29423	29278	29370	29283
61004	29259	227	0	0	8	0	0	2	0	0	0	48	1	0	0	4590	28879	0	0	24327	1000	1000	1000	5000	0	5	0	0	15940	28386	29373	3	10	1000	1000	2000	29051	29154	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	2	0	0	0	12984	9380	6937	3106	0	52	21767	3140	3819	15	50	57	28571	16046	13691	15389	1000	29270	29349	29275	29363	29277
61004	29311	228	0	0	6	0	0	6	0	0	0	39	0	0	0	4540	28829	0	0	24337	1000	1000	1000	5000	0	5	0	0	15965	28457	29289	3	29	1000	1000	2000	29181	29183	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	3	1000	0	3	0	0	0	13045	9370	6956	3091	1	50	21620	3206	3815	4	58	57	28387	16313	13790	15557	1000	29334	29421	29314	29314	29235

Count: 8

Code:

  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]
  st1 { v0.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40051	299	0	0	0	0	87	3	1	1	40027	16	16	1	25	80100	100	80000	100	80000	500	1840028	40018	40042	40042	29967	3	30001	80100	200	80000	200	160000	40054	40043	1	1	80201	100	99	100	100	80000	80000	100	80014	0	44	0	0	80002	0	0	2	80002	2	44	0	1	5110	1	16	1	1	40060	80000	100	40044	40043	40044	40056	40043
80204	40042	300	0	0	0	0	9	3	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40029	40042	40043	29956	3	30000	80100	200	80000	200	160000	40042	40047	1	1	80201	100	99	100	100	80000	80000	100	80000	14	42	0	0	80002	0	0	2	80002	2	0	14	0	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40043	40043
80204	40054	299	0	0	0	0	12	3	0	1	40027	16	16	1	25	80100	100	80000	100	80000	500	1840028	40017	40042	40040	30187	3	30000	80100	200	80000	200	160000	40063	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	44	0	0	80002	0	0	18	80002	16	42	0	3	5110	3	25	1	1	40037	80000	100	40043	40044	40043	40043	40041
80204	40042	299	1	0	0	0	0	3	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40047	40043	29956	3	30000	80100	200	80000	200	160000	40042	40052	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80000	0	0	2	80002	2	42	0	0	5110	1	16	1	1	40037	80000	100	40055	40044	40043	40043	40055
80204	40042	300	0	0	0	0	9	3	0	0	40025	0	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40066	29955	3	30011	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	1	0	18	80002	16	42	0	0	5110	1	17	1	1	40040	80000	100	40044	40053	40043	40044	40043
80204	40042	300	1	0	0	0	0	21	0	0	40032	16	16	0	25	80100	100	80000	100	80000	500	1840024	40017	40054	40044	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80016	0	0	11	80002	2	42	0	0	5110	1	16	1	1	40051	80000	100	40055	40043	40055	40043	40055
80204	40042	300	0	0	0	0	0	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	40017	40042	40052	29976	3	30012	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80015	0	42	0	1	80002	0	0	2	80002	2	44	0	0	5110	1	16	1	1	40051	80000	100	40043	40053	40043	40052	40044
80204	40042	300	0	0	1	0	0	20	0	0	40037	0	0	2	25	80100	100	80000	100	80000	500	1839448	40029	40042	40044	29955	3	29998	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	14	42	0	0	80016	0	1	0	80002	2	42	14	0	5110	1	16	1	1	40039	80000	100	40043	40043	40055	40043	40044
80204	40054	299	0	0	0	0	0	3	1	1	40027	16	0	1	25	80100	100	80000	100	80000	500	1840052	40017	40043	40044	29967	3	29998	80100	200	80000	200	160000	40054	40043	1	1	80201	100	99	100	100	80000	80000	100	80014	0	44	0	0	80002	0	0	0	80000	2	44	0	1	5110	1	16	1	1	40051	80000	100	40043	40043	40044	40055	40044
80204	40042	300	0	0	1	0	0	3	0	0	40027	16	16	6	25	80100	100	80000	100	80000	500	1839448	40029	40042	40044	29955	3	30000	80100	200	80000	200	160000	40042	40053	1	1	80201	100	99	100	100	80000	80000	100	80000	14	0	0	0	80002	1	0	6	80002	0	42	14	0	5110	1	16	1	1	40039	80000	100	40043	40044	40043	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40049	310	0	0	0	0	0	0	0	12	7	0	1	40027	0	0	0	25	80010	10	80000	10	80000	50	1839424	40017	40042	40042	29985	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	2	80002	2	34	0	5020	0	1	16	1	1	40039	0	0	80000	10	40043	40043	40043	40043	40043
80024	40042	310	0	0	0	0	0	0	0	0	3	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40049	40042	29977	3	30022	80010	20	80000	20	160000	40051	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	8	80002	2	34	0	5022	0	1	16	1	2	40039	0	0	80000	10	40051	40052	40052	40051	40043
80024	40050	310	0	0	0	0	0	0	0	0	6	0	0	40035	16	0	0	25	80010	10	80000	10	80000	50	1839352	40017	40042	40042	29977	3	30020	80010	20	80000	20	160000	40042	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	36	0	0	80002	0	0	2	80002	2	34	0	5020	0	2	16	1	2	40039	0	0	80000	10	40043	40043	40043	40043	40051
80024	40042	311	1	0	0	1	0	0	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40040	40042	29984	3	30020	80010	20	80000	20	160000	40042	40058	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80002	2	34	0	5022	0	1	16	1	1	40039	0	0	80000	10	40051	40052	40051	40051	40043
80024	40050	310	0	0	0	1	0	0	0	258	141	0	1	40173	16	16	0	25	80010	10	80000	10	80000	50	1839424	40025	40040	40042	29975	3	30031	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80002	0	34	0	5022	0	1	16	1	2	40039	0	0	80000	10	40043	40051	40041	40043	40043
80024	40042	310	0	0	0	0	0	0	0	45	88	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40040	40042	29975	3	30139	80010	20	80000	20	160000	40042	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	5022	0	1	16	2	2	40039	0	0	80000	10	40043	40043	40043	40183	40050
80024	40040	311	0	0	0	1	0	0	0	9	0	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40025	40042	40051	29984	3	30030	80010	20	80000	20	160000	40042	40051	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	1	0	8	80002	2	34	0	5022	0	1	16	2	1	40039	0	0	80000	10	40043	40043	40043	40043	40043
80024	40179	311	0	0	0	0	0	0	0	6	3	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	5022	0	2	16	2	2	40039	0	0	80000	10	40043	40043	40043	40041	40054
80024	40042	311	0	0	0	0	0	0	0	6	9	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839808	40017	40051	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	5	80002	2	34	0	5020	0	4	16	2	2	40039	0	0	80000	10	40043	40043	40043	40043	40043
80024	40042	310	1	0	0	0	0	0	0	12	0	0	1	40035	16	16	0	25	80010	10	80000	10	80000	50	1839424	40025	40042	40040	29975	3	30030	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	5	80002	2	34	0	5022	0	1	16	2	1	40039	0	0	80000	10	40043	40043	40043	40043	40043

ST1 (multiple, 1 reg, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations