Firestorm: ST1 (multiple, 1 reg, 2S) measurements

Code:

  st1 { v0.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29499	238	0	2	0	1	0	12	1	1	0	4640	29011	1	0	24262	1000	1000	1000	5000	5	15976	28299	29407	3	10	1000	1000	2000	29107	29162	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	1000	0	0	12746	9157	6865	3025	0	51	21677	3082	3816	13	59	60	28324	16321	13507	15725	1000	29258	29304	29146	29230	29238
61004	29234	219	0	1	0	1	0	0	1	0	0	4546	28786	0	1	24277	1000	1000	1000	5000	6	15959	28274	29340	3	10	1000	1000	2000	29116	29041	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	1000	2	0	12877	9005	6829	3070	0	56	21712	3044	3816	14	56	52	28404	16304	13617	15754	1000	29300	29178	29301	29335	29276
61004	29230	219	0	1	0	0	0	0	1	0	0	4548	28824	0	1	24307	1000	1000	1000	5000	6	15973	28391	29271	3	10	1000	1000	2000	29194	29201	1	1	61001	1000	1000	1000	0	3	0	1000	0	6	1000	0	0	12804	9090	6843	3025	1	50	21677	3032	3813	19	57	53	28399	16409	13841	15594	1000	29311	29293	29258	28983	29265
61004	29319	219	0	2	0	1	0	0	1	0	0	4532	28875	0	0	24286	1000	1000	1000	5000	1	15953	28330	29381	3	10	1000	1000	2000	29059	29076	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	1000	2	0	12936	9120	6857	3090	2	58	21705	3055	3822	12	60	57	28363	16328	13712	15960	1000	29295	29422	29390	29268	29360
61004	29267	220	0	2	0	1	0	0	1	0	0	4582	28776	0	0	24282	1000	1000	1000	5000	5	15963	28379	29382	3	10	1000	1000	2000	29144	29122	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	2	0	12973	8985	6885	3060	2	54	21746	3014	3815	13	58	57	28459	16476	13752	15768	1000	29344	29172	29309	29274	29366
61004	29300	219	0	1	0	1	0	0	1	1	0	4492	28848	0	0	24424	1000	1000	1000	5000	1	15953	28379	29355	3	10	1000	1000	2000	29182	29195	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	2	0	12866	9203	6853	3054	1	54	21722	3047	3818	11	57	50	28457	16327	13752	15813	1000	29327	29349	29389	29344	29338
61004	29245	220	0	2	0	3	0	0	1	0	0	4606	28905	0	0	24409	1000	1000	1000	5000	3	15955	28434	29289	3	10	1000	1000	2000	29210	29146	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	2	0	12887	8965	6816	3038	1	55	21702	3084	3821	13	53	53	28410	16179	13890	15744	1000	29250	29321	29347	29383	29409
61004	29252	219	0	3	0	2	0	0	1	0	0	4635	28804	0	0	24334	1000	1000	1000	5000	1	15966	28394	29322	3	10	1000	1000	2000	29141	29244	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	2	0	12816	9111	6863	3062	1	60	21654	3007	3820	11	57	59	28430	16429	13799	15757	1000	29331	29408	29265	29389	29275
61004	29242	219	0	1	0	1	0	0	1	0	0	4592	28825	0	0	24338	1000	1000	1000	5000	0	15965	28342	29309	3	10	1000	1000	2000	29211	29089	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	0	0	12779	9034	6843	3059	1	54	21686	3010	3823	16	56	56	28435	16349	13797	15768	1000	29331	29342	29351	29296	29385
61004	29306	220	0	2	0	1	0	0	1	0	0	4548	28813	0	0	24291	1000	1000	1000	5000	0	15970	28398	29370	3	10	1000	1000	2000	29128	29154	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	1000	0	0	12840	9036	6841	3088	0	58	21803	3036	3818	11	62	51	28379	16401	13872	15679	1000	29298	29355	29356	29347	29299

Count: 8

Code:

  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]
  st1 { v0.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	310	0	0	0	0	0	0	0	15	3	0	0	40028	16	0	1	25	80160	100	80000	100	80000	500	1839448	0	40017	40042	40043	29955	3	30010	80100	200	80000	200	160242	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	1	0	5	80002	2	42	0	5110	3	16	3	3	40040	0	0	80000	100	40044	40043	40044	40043	40041
80204	40043	310	0	0	0	0	1	0	0	0	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	0	41556	40042	40042	29955	3	30001	80100	200	80000	200	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	3	80002	2	42	0	5150	5	16	6	5	40039	0	0	80000	100	40043	40043	40043	40043	40043
80204	40040	311	0	0	0	0	0	0	0	0	3	0	0	40028	16	16	74	25	80100	100	80000	100	80000	500	1839448	0	40017	40042	40042	29955	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	2	80002	2	42	0	5110	3	25	3	2	40040	0	0	80000	100	40043	40044	40043	40044	40043
80204	40040	310	0	0	0	0	0	0	0	0	3	0	0	40028	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	40017	40042	40043	29967	3	30000	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	3	80002	2	42	0	5110	3	16	3	3	40040	0	0	80000	100	40045	40041	40043	40041	40044
80204	40042	310	0	0	0	0	0	0	0	0	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	40018	40042	40043	29955	3	30000	80100	200	80000	200	160000	40054	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	44	0	0	80002	0	0	2	80002	2	0	0	5110	3	16	3	3	40039	0	0	80000	100	40043	40043	40043	40044	40043
80204	40043	310	0	0	0	0	0	1	1	0	3	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839472	0	40017	40054	40042	29955	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80000	2	42	0	5110	2	16	2	3	40037	0	0	80000	100	40044	40043	40044	40043	40055
80204	40042	310	0	0	0	0	0	0	0	0	3	0	0	40027	16	16	91	55	80220	100	80060	100	80108	500	1847653	0	40154	40256	40198	30061	16	30201	80208	200	80125	200	160480	40252	40248	3	1	80201	100	99	100	100	80000	80000	100	80120	0	42	31	0	80122	0	4	882	80062	2	42	0	5130	5	25	4	5	40039	0	0	80000	100	40045	40044	40045	40041	40044
80204	40040	310	0	0	0	0	0	0	0	0	3	0	0	40028	0	16	1	25	80100	100	80000	100	80000	500	1839472	0	40017	40043	40042	29955	3	30000	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5110	2	16	3	5	40037	0	0	80000	100	40043	40045	40043	40043	40041
80204	40040	310	0	0	0	0	0	0	0	0	0	0	0	40025	16	0	0	25	80100	100	80000	100	80000	500	1839472	0	40017	40042	40040	29955	3	30002	80100	200	80000	200	160000	40054	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	5	80002	0	42	0	5110	2	16	3	3	40039	0	0	80000	100	40043	40043	40043	40041	40041
80204	40042	310	0	0	0	0	0	0	0	0	7	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839352	0	40017	40042	40042	29953	3	30001	80100	200	80000	200	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	6	80002	2	42	0	5110	3	16	3	2	40037	0	0	80000	100	40044	40043	40041	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd store (99)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e8	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40057	311	1	0	1	1	1	0	0	0	19	0	0	1	40032	16	16	5	25	80010	10	80000	10	80000	50	1839692	40025	40053	40047	29985	3	30038	80010	20	80000	20	160000	40051	40057	1	1	80021	10	9	10	10	0	80000	80000	0	10	80014	14	36	0	0	80016	0	0	17	80002	16	36	14	0	0	5020	0	4	16	4	3	40049	0	80000	10	40053	40059	40048	40062	40060
80024	40053	310	1	0	0	0	1	0	0	0	19	0	0	1	40037	16	16	4	25	80010	10	80000	10	80000	50	1839692	40033	40052	40050	29992	3	30030	80010	20	80000	20	160000	40047	40052	1	1	80021	10	9	10	10	0	80000	80000	0	10	80014	15	36	2	0	80016	1	0	23	80002	16	0	14	0	0	5020	1	3	16	4	3	40050	0	80000	10	40053	40061	40053	40053	40059
80024	40049	311	1	0	0	0	0	0	0	0	14	0	0	1	40043	16	0	10	25	80010	10	80000	10	80000	50	1839812	40034	40051	40059	29994	3	30040	80010	20	80000	20	160000	40052	40051	1	1	80021	10	9	10	10	0	80000	80000	0	10	80014	15	36	0	0	80016	2	1	19	80002	16	36	14	0	0	5021	0	5	16	4	3	40049	0	80000	10	40053	40059	40051	40199	40059
80024	40047	310	1	0	1	0	0	0	0	0	17	0	0	1	40038	16	16	5	25	80010	10	80060	10	80000	50	1839932	40022	40047	40047	29994	3	30027	80010	20	80000	20	160000	40197	40052	1	1	80021	10	9	10	10	0	80000	80000	0	10	80015	14	36	0	0	80016	0	0	18	80002	14	36	14	0	0	5020	0	3	16	3	4	40044	0	80000	10	40054	40061	40052	40054	40060
80024	40047	311	1	0	0	1	0	0	0	0	19	0	0	1	40044	16	16	6	25	80010	10	80000	10	80000	50	1839812	40023	40050	40048	29982	3	30027	80010	20	80000	20	160000	40052	40050	1	1	80021	10	9	10	10	0	80000	80000	0	10	80015	14	34	0	0	80002	1	0	2	80002	2	34	0	0	0	5021	0	4	16	3	4	40039	0	80000	10	40043	40041	40043	40044	40052
80024	40042	311	0	0	0	0	0	0	0	6	3	0	0	0	40027	0	16	8	25	80010	10	80000	10	80000	50	1839692	40033	40188	40058	29992	3	30029	80010	20	80000	20	160000	40052	40047	1	1	80021	10	9	10	10	0	80000	80000	0	10	80016	14	34	0	0	80014	1	1	20	80000	16	0	14	1	0	5020	0	2	16	4	2	40050	0	80000	10	40048	40048	40041	40043	40043
80024	40042	311	0	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	10	0	80000	80000	0	10	80000	14	36	0	1	80076	1	0	14	80002	16	36	14	1	0	5020	0	3	16	3	3	40044	0	80000	10	40060	40052	40054	40053	40050
80024	40197	311	1	0	0	1	1	0	0	0	18	1	0	1	40044	0	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	0	80000	80000	0	10	80000	0	34	0	0	80002	2	0	2	80002	2	34	0	0	0	5020	0	3	16	3	3	40039	0	80000	10	40043	40061	40051	40051	40049
80024	40052	310	1	0	0	0	1	0	0	0	14	0	0	1	40043	16	16	2	25	80010	10	80000	10	80000	50	1839692	40036	40053	40047	29994	3	30030	80010	20	80000	20	160000	40058	40052	1	1	80021	10	9	10	10	0	80000	80000	0	10	80015	14	34	0	0	80002	0	0	2	80002	2	34	0	0	0	5020	0	3	16	4	3	40039	0	80000	10	40043	40059	40063	40041	40043
80024	40051	310	0	0	0	0	0	0	0	0	3	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	40025	40042	40040	29986	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	0	80000	80000	0	10	80780	14	36	0	0	80002	1	0	0	80002	2	40	0	0	0	5039	0	3	16	4	3	40039	0	80000	10	40043	40051	40041	40051	40043

ST1 (multiple, 1 reg, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations