Firestorm: ST1 (multiple, 1 reg, 4H) measurements

Code:

  st1 { v0.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29197	226	23	0	0	18	0	0	0	0	4687	28384	1	0	23884	1000	1000	1000	5000	0	0	0	0	15972	28368	29149	3	10	1000	1000	2000	28955	28908	1	1	61001	1000	1000	1000	2	0	1000	0	0	1000	2	13586	9696	6889	3145	6	54	21271	3247	3815	44	47	48	28223	15532	13258	15345	1000	28784	28848	28721	28845	28884
61004	28960	223	22	0	0	23	0	27	0	0	4764	28721	1	0	24108	1000	1000	1000	5000	0	10	0	9	15941	28251	29207	3	10	1000	1000	2000	28855	28720	1	1	61001	1000	1000	1000	0	0	1000	0	0	1000	3	13410	9835	6995	3237	12	54	21505	3227	3816	49	47	48	28267	15843	13363	15358	1000	29061	29096	28888	29101	28950
61004	28803	224	19	0	0	22	0	0	0	0	4762	28588	0	0	24010	1000	1000	1000	5000	0	6	0	0	15966	28344	29121	3	10	1000	1000	2000	28808	28780	1	1	61001	1000	1000	1000	2	0	1000	0	0	1000	3	13321	9851	6887	3218	7	46	21525	3211	3822	47	64	57	28374	15739	13038	15092	1000	29116	29024	28948	28848	29102
61004	28880	225	22	0	0	16	0	0	0	0	4535	28569	0	1	24181	1000	1000	1000	5000	0	0	1	0	15959	28431	29130	3	10	1000	1001	2000	28930	28951	1	1	61001	1000	1000	1000	0	0	1000	0	0	1000	2	13153	9178	6830	3129	9	50	21577	3227	3816	49	59	53	28635	15904	13545	15573	1000	29179	29192	29167	29224	30182
61004	29235	235	16	1	0	23	0	0	0	0	4598	28762	1	0	24337	1000	1001	1000	5000	0	4	1	0	15962	28343	29172	3	10	1000	1000	2000	28895	28908	1	1	61001	1000	1000	1000	2	0	1000	0	455	1000	0	13130	9382	6843	3153	9	51	21539	3211	3819	44	54	57	28394	16015	13428	15688	1000	29215	29135	29181	29152	29168
61004	29178	226	21	0	0	19	1	0	1	0	4639	28611	0	0	24273	1000	1000	1000	5000	0	0	0	0	15956	28289	29197	3	10	1000	1000	2000	28963	28834	1	1	61001	1000	1000	1000	2	0	1002	0	0	1000	2	13096	9254	6874	3045	7	47	21500	3109	3817	45	51	51	28453	16072	13241	15380	1000	29204	29145	29124	29130	29140
61004	29025	227	19	0	0	16	0	0	88	0	4675	28609	0	0	24168	1000	1001	1000	5000	0	4	0	8	15969	28303	29156	3	10	1000	1000	2000	28941	29017	1	1	61001	1000	1000	1000	2	0	1000	0	0	1000	2	13152	9179	6897	3090	9	43	21441	3214	3815	42	49	52	28344	15957	13401	15079	1000	29090	29095	29153	29209	28980
61004	29174	225	22	0	0	17	1	0	1	0	4598	28592	0	1	24130	1000	1000	1000	5000	0	1	0	0	15962	28338	29223	3	10	1000	1000	2000	29026	28894	1	1	61001	1000	1000	1000	3	0	1000	0	0	1000	2	13252	9465	6806	3121	14	50	21504	3268	3818	46	52	48	28449	15742	13249	15394	1000	29154	28963	28988	29125	29108
61004	29144	225	19	0	1	19	0	0	0	0	4613	28644	0	0	24208	1000	1000	1000	5005	0	2	0	0	15952	28338	29068	8	10	1000	1000	2000	28994	29044	1	1	61001	1000	1000	1000	3	0	1000	0	0	1000	2	13162	9303	6858	3132	13	52	21520	3262	3810	48	53	50	28499	16030	13463	15512	1000	29067	29074	29201	29170	29126
61004	29112	226	21	0	0	19	0	132	0	0	4591	28675	0	0	24086	1000	1000	1000	5000	0	0	0	8	15952	28347	29062	3	10	1000	1000	2000	28931	28815	1	1	61001	1000	1000	1000	3	2	1000	0	0	1000	0	13181	9186	6832	3156	8	47	21489	3213	3816	38	44	57	28338	15806	13313	15379	1000	29085	29094	29053	29044	29154

Count: 8

Code:

  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40063	300	1	0	0	0	0	0	19	0	0	1	40039	16	16	2	25	80100	100	80000	100	80000	500	1840438	0	40029	40054	40055	29964	3	30021	80100	200	80000	200	160000	40052	40063	1	1	80201	100	99	100	100	80000	80000	100	80015	14	42	0	0	80016	0	2	17	80002	16	44	14	0	0	5110	3	16	2	4	40061	80000	100	40055	40055	40055	40055	40055
80204	40054	300	1	0	0	0	0	9	19	0	0	1	40036	16	16	5	25	80100	100	80000	100	80000	500	1840460	0	40029	40054	40053	29965	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	15	44	0	2	80016	0	0	17	80002	16	44	14	0	0	5110	2	16	3	3	40051	80000	100	40053	40048	40052	40053	40055
80204	40053	300	1	1	1	0	0	0	14	0	0	1	40037	15	16	1	25	80100	100	80000	100	80000	500	1840028	0	40029	40054	40053	29965	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	2	80016	0	1	19	80002	16	0	14	0	0	5110	3	16	3	3	40051	80000	100	40055	40055	40055	40055	40054
80204	40054	300	1	0	1	1	0	51	18	0	0	1	40049	16	16	1	25	80100	100	80000	100	80000	500	1840028	0	40028	40054	40052	29976	16	30240	80752	200	80000	200	160000	40054	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	1	80016	0	1	18	80002	16	44	14	1	0	5110	3	16	3	3	40061	80000	100	40055	40056	40055	40055	40055
80204	40063	300	1	0	0	0	0	360	19	0	0	1	40037	16	16	6	25	80100	100	80000	100	80000	500	1840438	0	40029	40052	40063	29968	3	30010	80100	200	80000	200	160000	40052	40055	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	0	80016	2	0	19	80002	16	42	14	0	0	5110	3	16	3	3	40051	80000	100	40055	40055	40055	40055	40052
80204	40054	300	1	1	1	1	0	0	18	0	0	1	40037	0	16	4	25	80100	100	80000	100	80000	500	1839956	0	40029	40064	40054	29967	3	30012	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	0	80016	0	1	16	80000	16	44	14	0	0	5110	4	16	3	3	40051	80000	100	40055	40055	40055	40055	40053
80204	40054	300	1	1	0	1	0	0	14	0	0	1	40039	16	16	4	25	80100	100	80000	100	80000	500	1839908	0	40029	40063	40055	29967	3	30012	80100	200	80000	200	160000	40055	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	1	1	80016	0	1	18	80002	16	44	14	0	0	5110	3	16	4	4	40051	80000	100	40053	40052	40048	40048	40064
80204	40054	300	1	0	0	0	0	0	19	0	0	1	40036	16	0	2	25	80100	100	80000	103	80000	500	1840028	1	40030	40054	40055	29967	3	30012	80100	200	80000	200	160000	40063	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	0	0	80016	0	1	16	80002	16	44	14	1	0	5110	3	16	3	3	40051	80000	100	40053	40054	40053	40053	40064
80204	40047	300	1	1	0	0	0	0	22	0	0	1	40039	16	16	4	25	80100	100	80000	100	80000	500	1839956	0	40029	40063	40054	29967	3	30012	80100	200	80000	200	160000	40064	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	1	0	80016	2	1	21	80002	16	44	14	0	0	5110	3	16	3	2	40051	80000	100	40053	40054	40054	40053	40064
80204	40054	300	1	0	0	1	0	36	19	1	0	1	40039	16	16	3	25	80100	100	80000	100	80000	500	1839956	0	40029	40054	40052	29961	3	30005	80100	200	80000	200	160000	40047	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	16	44	0	0	80016	0	0	18	80002	16	44	14	0	0	5110	3	16	3	2	40051	80000	100	40052	40053	40053	40054	40055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40058	322	1	0	1	0	0	1	0	0	3	0	0	40039	16	16	2	25	80010	10	80000	10	80000	50	1839448	0	40029	40055	40054	29989	3	30035	80010	20	80000	20	160000	40054	40052	1	1	80021	10	9	0	10	10	80000	80000	10	80014	0	42	0	1	80016	0	0	16	80002	16	44	14	0	0	5020	33	16	33	34	40051	0	80000	10	40045	40044	40043	40048	40043
80024	40043	310	1	0	1	0	1	0	0	0	0	0	1	40027	16	16	1	25	80010	10	80060	10	80000	50	1840028	0	40027	40054	40042	29977	3	30033	80010	20	80000	20	160000	40054	40055	1	1	80021	10	9	0	10	10	80000	80000	10	80000	14	43	0	2	80016	0	0	2	80002	16	44	14	0	0	5020	13	16	33	34	40039	0	80000	10	40049	40044	40043	40044	40048
80024	40054	311	0	0	0	0	0	0	0	0	0	0	1	40028	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40018	40054	40052	29977	3	30034	80010	20	80000	20	160000	40054	40052	1	1	80021	10	9	0	10	10	80000	80000	10	80000	0	42	0	0	80016	0	0	2	80002	0	44	14	0	0	5020	33	16	36	37	40040	0	80000	10	40043	40043	40043	40043	40045
80024	40054	310	1	0	0	0	1	0	0	0	17	0	0	40036	16	16	5	25	80010	10	80000	10	80000	50	1839448	0	40017	40192	40055	29989	3	30023	80010	20	80000	20	160000	40042	40063	1	1	80021	10	9	0	10	10	80000	80000	10	80015	14	44	0	0	80016	0	0	18	80001	2	44	14	1	0	5020	44	16	36	36	40051	0	80000	10	40043	40043	40055	40043	40055
80024	40052	311	0	0	1	0	1	0	0	0	91	0	1	40040	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40027	40055	40052	29998	16	30032	80010	20	80000	20	160000	40054	40053	1	1	80021	10	9	0	10	10	80000	80000	10	80015	0	42	0	0	80016	0	1	17	80002	16	44	14	1	0	5020	33	16	14	34	40051	0	80000	10	40044	40043	40046	40194	40047
80024	40054	310	1	0	0	0	0	0	0	0	17	0	1	40030	16	16	1	55	80010	10	80000	10	80000	50	1839592	0	40021	40052	40054	29990	3	30020	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	0	10	10	80000	80000	10	80014	14	42	0	0	80000	1	0	21	80002	2	42	14	0	0	5020	15	16	14	33	40039	0	80000	10	40130	40044	40044	40043	40055
80024	40054	310	0	0	0	0	1	0	0	0	3	0	1	40048	16	16	1	25	80010	10	80000	10	80000	50	1840028	0	40029	40042	40054	29989	3	30034	80010	20	80000	20	160000	40063	40043	1	1	80021	10	9	0	10	10	80000	80000	10	80015	14	46	0	2	80002	0	0	16	80002	16	42	0	0	0	5020	33	16	34	35	40051	1	80000	10	40064	40055	40065	40064	40043
80024	40051	310	1	0	0	0	0	0	0	0	17	0	0	40036	16	16	5	25	80010	10	80000	10	80000	50	1839934	0	40017	40052	40047	29989	3	30022	80010	20	80000	20	160000	40040	40064	1	1	80021	10	9	0	10	10	80000	80000	10	80000	0	42	1	1	80016	0	0	2	80002	16	42	0	0	0	5020	34	16	33	33	40039	0	80000	10	40044	40043	40187	40064	40043
80024	40042	310	1	0	0	0	0	0	0	12	17	0	1	40037	0	16	9	25	80010	10	80000	10	80000	50	1839448	0	40038	40053	40063	29998	3	30032	80010	20	80000	20	160000	40054	40052	1	1	80021	10	9	0	10	10	80000	80000	10	80014	0	42	4	0	80002	0	0	14	80002	16	46	14	0	0	5020	31	24	36	37	40051	0	80000	10	40056	40053	40052	40054	40044
80024	40054	311	1	0	0	0	0	0	0	0	17	0	1	40028	16	16	2	25	80010	10	80000	10	80000	50	1839472	0	40027	40054	40042	29978	3	30034	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	0	10	10	80000	80000	10	80015	15	42	0	0	80002	0	0	18	80002	2	42	14	0	0	5020	34	16	13	33	40040	0	80000	10	40053	40043	40041	40043	40055

ST1 (multiple, 1 reg, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations