Firestorm: ST1 (multiple, 1 reg, 4S) measurements

Code:

  st1 { v0.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29142	235	3	2	0	0	0	0	0	0	0	1	0	0	0	4564	28511	0	1	24102	1000	1001	1000	5000	7	15948	28306	29087	3	10	1000	1000	2000	28876	28937	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	0	0	13222	9115	6881	3138	1	59	21383	3193	3809	35	61	66	28305	15966	13112	15428	1000	28891	29086	29168	29088	29130
61004	29053	234	0	1	0	0	0	1	0	0	0	0	0	0	0	4743	28639	1	0	24076	1000	1000	1000	5000	9	15953	28345	29166	3	10	1000	1000	2000	28893	28827	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	0	0	12967	9483	6947	3116	0	53	21357	3226	3808	34	62	67	28382	15756	13045	15122	1000	29022	29042	29169	28983	28952
61004	29097	233	0	1	0	0	2	0	0	0	6	0	0	0	0	4735	28557	0	0	24125	1000	1000	1000	5000	12	15928	28139	29095	3	10	1000	1000	2000	28850	28899	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	3	0	0	13314	9487	6855	3161	1	66	21478	3200	3805	35	58	63	28364	16014	13541	15385	1000	29046	29061	28869	29094	28978
61004	28970	234	0	1	1	1	1	0	0	0	0	0	0	0	0	4717	28627	0	0	23977	1000	1000	1000	5000	9	15933	28086	29027	3	10	1000	1000	2000	28883	28877	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	3	1000	2	0	190	13126	9278	6965	3155	0	61	21276	3158	3804	37	57	62	28348	16016	13368	15312	1000	29033	29173	29117	29019	29075
61004	29089	234	1	1	0	0	1	0	0	0	12	0	1	0	0	4785	28532	0	1	24026	1000	1000	1000	5000	7	15962	28277	29100	3	10	1000	1000	2000	28865	28899	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	0	0	0	13144	9410	6892	3136	0	63	21446	3177	3812	36	60	66	28359	16034	13326	15232	1000	29207	29159	29096	29094	28981
61004	29200	234	0	0	0	0	1	0	0	0	0	0	0	0	0	4669	28574	1	0	24093	1000	1000	1000	5000	1	15932	28358	29073	3	10	1000	1000	2000	28870	28894	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	3	1000	3	0	0	13323	9473	6933	3101	0	56	21518	3180	3814	43	60	55	28357	15960	13583	15018	1000	29137	29089	28922	29034	29122
61004	29050	234	0	1	0	0	1	0	0	0	12	0	0	0	0	4577	28469	0	0	24135	1000	1000	1000	5000	10	15960	28240	28982	3	10	1000	1000	2000	28924	28877	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	0	0	13401	9367	6873	3175	0	65	21482	3250	3819	39	54	64	28417	16070	13063	15395	1000	29070	29029	29205	29196	28872
61004	29068	234	1	1	0	0	1	0	0	0	138	0	0	0	0	4718	28572	0	0	24055	1000	1000	1000	5000	2	15941	28231	29088	3	10	1000	1000	2000	28889	28924	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	0	1000	2	0	0	13187	9228	6929	3178	1	57	21426	3226	3818	41	57	62	28364	15899	13483	15011	1000	29098	29178	29028	29038	29169
61004	29050	233	0	1	0	0	1	0	0	0	0	0	0	0	0	4592	28566	0	0	24047	1000	1000	1000	5000	0	15943	28394	29041	3	10	1000	1000	2000	28936	28952	1	1	61001	1000	1000	1000	0	3	0	1000	0	0	0	1000	2	0	0	13281	9177	6888	3211	0	60	21423	3210	3810	41	67	67	28383	16085	13267	15334	1000	28983	29158	29100	29163	28945
61004	29038	233	1	2	0	0	1	0	0	0	0	0	0	0	0	4607	28627	0	0	24140	1000	1000	1000	5000	13	15944	28299	29007	3	10	1000	1000	2000	28932	28856	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	0	0	13114	9353	6931	3131	2	55	21416	3217	3811	41	60	65	28343	15885	13379	15409	1000	28956	29185	29108	29191	29095

Count: 8

Code:

  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40047	321	1	1	0	0	0	0	15	18	0	1	40040	16	16	2	25	80100	100	80000	100	80000	500	1839981	0	40030	40052	40054	29967	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	1	80016	1	1	19	80002	16	48	14	0	5110	1	16	1	2	40061	80000	100	40055	40064	40065	40049	40055
80204	40052	322	1	0	1	0	0	0	3	17	0	1	40039	0	16	5	25	80100	100	80000	100	80000	500	1839934	0	40029	40052	40054	29968	3	30012	80100	200	80000	200	160000	40052	40064	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	0	80014	0	1	16	80002	16	44	14	0	5110	1	16	1	1	40050	80000	100	40054	40054	40055	40055	40053
80204	40054	322	1	1	0	0	0	0	3	17	0	1	40039	0	16	1	25	80100	100	80000	100	80000	500	1840460	0	40030	40052	40055	29968	3	30022	80100	200	80000	200	160000	40054	40063	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	0	80016	0	1	16	80002	16	44	14	0	5110	1	16	1	1	40051	80000	100	40055	40055	40055	40055	40053
80204	40054	322	1	0	0	0	0	0	3	22	1	1	40040	16	16	2	25	80100	100	80000	100	80000	500	1839933	0	40029	40052	40054	29967	3	30022	80100	200	80000	200	160000	40053	40056	1	1	80201	100	99	100	100	80000	80000	100	80014	14	48	0	1	80016	1	1	19	80002	16	44	14	0	5110	1	16	1	1	40051	80000	100	40055	40055	40055	40055	40053
80204	40054	322	1	0	1	0	0	0	0	20	0	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1840076	0	40027	40054	40052	29965	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	15	44	1	0	80016	0	0	18	80002	16	44	14	1	5110	1	16	1	1	40051	80000	100	40055	40055	40055	40055	40057
80204	40055	322	1	0	0	0	0	0	18	17	0	1	40039	16	16	6	25	80100	100	80000	100	80000	500	1839956	0	40038	40054	40063	29976	3	30012	80100	200	80000	200	160000	40054	40053	1	1	80201	100	99	100	100	80000	80000	100	80015	16	44	0	1	80016	0	1	19	80002	16	44	14	1	5110	1	16	1	1	40044	80000	100	40055	40055	40055	40055	40056
80204	40054	321	1	0	0	0	0	0	15	17	1	1	40038	0	16	2	25	80100	100	80000	100	80000	500	1840004	0	40028	40054	40053	29965	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	14	44	0	1	80016	0	1	16	80002	16	44	14	1	5110	1	16	1	1	40051	80000	100	40055	40055	40055	40056	40055
80204	40063	321	1	1	1	0	0	0	168	17	0	1	40037	16	16	2	25	80100	100	80000	100	80000	500	1839956	0	40038	40054	40063	29976	3	30010	80100	200	80000	200	160000	40054	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	1	80016	1	0	22	80002	16	44	14	1	5110	1	16	1	1	40051	80000	100	40048	40048	40055	40055	40055
80204	40052	322	1	0	0	0	0	0	15	17	0	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1840052	0	40029	40056	40054	29967	3	30012	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	0	80016	0	0	17	80002	16	42	14	1	5110	1	16	1	2	40049	80000	100	40053	40053	40052	40053	40055
80204	40053	322	1	0	1	0	0	0	3	17	0	1	40039	16	16	0	25	80100	100	80000	100	80000	500	1839884	0	40030	40052	40054	29968	3	30010	80100	200	80000	200	160000	40054	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	1	80016	0	2	22	80002	16	44	14	0	5110	1	16	1	1	40049	80000	100	40053	40054	40054	40053	40053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40043	321	0	0	0	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	40017	40043	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5020	1	2	16	1	1	40039	80000	10	40043	40043	40043	40043	40043
80024	40042	310	0	0	0	0	0	3	40027	16	16	8	25	80010	10	80000	10	80000	50	1839472	1	40018	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	42	0	5020	1	1	16	1	1	40040	80000	10	40043	40043	40043	40043	40043
80024	40042	311	0	0	0	0	0	3	40028	0	0	0	25	80010	10	80000	10	80000	50	1839496	1	40017	40043	40042	29977	3	30023	80010	20	80000	20	160000	40043	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5020	0	2	16	1	1	40039	80000	10	40043	40043	40043	40043	40043
80024	40042	310	0	0	0	0	0	3	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	40018	40043	40040	29977	3	30022	80010	20	80000	20	160000	40042	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80000	2	42	0	5020	0	1	16	2	1	40039	80000	10	40043	40043	40043	40043	40043
80024	40043	310	0	0	0	0	12	135	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	40017	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40046	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	5	80002	2	42	0	5020	0	2	16	1	1	40040	80000	10	40044	40043	40043	40043	40043
80024	40042	310	0	0	0	0	12	3	40027	16	16	330	25	80010	10	80180	10	80432	50	1853743	1	40255	40182	40042	30346	16	30486	80334	20	80242	20	160484	40183	40182	3	1	80021	10	9	10	10	80000	80000	10	80060	0	0	60	0	80182	0	2	792	80180	2	42	2	5057	0	2	33	3	1	40039	80000	10	40044	40043	40044	40182	40182
80024	40739	325	0	1	3	3	402	443	40305	16	16	219	115	80190	10	80180	10	80324	50	1844293	1	40340	40458	40459	30255	42	30151	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5020	0	2	16	1	1	40039	80000	10	40041	40041	40043	40044	40043
80024	40042	322	0	0	0	0	12	3	40027	16	16	0	25	80010	10	80000	10	80000	50	1839472	1	40015	40044	40040	29978	3	30023	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80060	2	44	30	0	80122	0	0	2080	80002	2	42	2	5020	0	2	16	1	1	40039	80000	10	40046	40043	40044	40041	40043
80024	40042	321	0	0	0	0	0	3	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	40017	40054	40043	29978	3	30023	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	48	0	0	80062	2	2	2	80002	2	44	0	5020	0	2	16	1	2	40413	80000	10	40041	40192	40043	40437	40044
80024	40040	311	0	0	0	0	0	3	40027	16	16	0	25	80010	10	80000	10	80324	50	1839448	1	40017	40042	40043	29977	3	30023	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	5	80002	0	42	0	5020	0	2	16	2	1	40039	80000	10	40044	40043	40044	40043	40043

ST1 (multiple, 1 reg, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations