Firestorm: ST1 (multiple, 1 reg, 8B) measurements

Code:

  st1 { v0.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	29400	228	27	0	0	29	0	1	0	132	0	0	0	4618	28808	0	1	24320	1000	1000	1000	5000	13	0	0	15938	28402	29217	3	10	1000	1000	2000	29146	29117	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	3	0	0	13044	9391	6895	3048	12	64	21638	3290	3803	11	55	50	28496	16237	13585	15281	1000	29291	29273	29292	29274	29341
61004	29254	228	22	0	0	27	0	0	0	0	1	0	0	4534	28808	1	1	24335	1000	1000	1000	5000	14	0	0	15943	28317	29307	3	10	1000	1000	2000	29165	29126	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	3	1000	0	0	0	12965	9301	6884	3038	14	46	21674	3164	3799	15	52	54	28436	16205	13717	15690	1000	29273	29239	29322	29270	29265
61004	29416	227	23	0	0	21	0	0	0	0	0	0	0	4615	28968	0	0	24442	1000	1000	1000	5000	15	0	0	16180	28264	29072	3	10	1000	1000	2000	28743	28698	1	1	61001	1000	1000	1000	0	3	0	1000	11	0	3	1000	0	0	0	13485	9815	7054	3224	15	48	21083	3211	3813	14	56	54	28063	15261	12912	14802	1000	28680	28705	28762	28664	28894
61004	28796	222	19	0	0	17	0	0	0	0	0	0	1	4730	28287	0	1	23674	1001	1000	1000	5000	9	1	0	15935	28079	28564	3	10	1000	1000	2000	28658	28597	1	1	61001	1000	1000	1000	0	0	0	1000	0	0	0	1000	2	0	0	13153	9622	7051	3227	14	56	20896	3180	3811	19	52	60	28029	15219	12962	14737	1000	28681	28774	28653	28571	28629
61004	28617	222	19	0	0	25	0	0	0	12	0	0	0	4876	28322	1	0	23681	1000	1000	1000	5000	10	0	0	15984	27957	28631	3	29	1001	1001	2000	28528	28505	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	0	0	13423	9837	6954	3191	13	54	21135	3210	3816	15	47	48	28079	15245	12819	14985	1000	28816	28707	28762	28581	28640
61004	28761	222	17	0	0	26	0	0	0	0	0	0	0	4798	28398	0	0	23736	1000	1000	1000	5000	5	0	0	15970	28137	28702	3	10	1000	1000	2000	28492	28460	1	1	61001	1000	1000	1002	0	0	0	1000	0	0	0	1000	2	0	0	13309	9445	6900	3191	16	46	21095	3161	3809	20	49	50	28089	15246	12772	14660	1000	28788	28640	28665	28772	28666
61004	28660	222	21	0	0	25	0	0	0	144	88	0	0	4659	28597	0	0	23876	1000	1000	1000	5000	5	0	0	15970	28158	28754	3	10	1000	1000	2000	28542	28066	1	1	61001	1000	1000	1000	0	2	0	1001	0	2	0	1001	3	0	0	13380	9630	6926	3229	9	57	20992	3150	3812	12	54	49	28174	15555	12886	14675	1000	28663	28666	28633	28664	28788
61004	28759	223	19	0	0	18	0	0	0	0	0	0	0	4743	28387	0	0	23668	1000	1000	1000	5000	2	1	0	15964	28057	28742	3	10	1000	1000	2000	28651	28584	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	0	0	0	13298	9667	7042	3199	16	56	21024	3094	3818	4	48	53	28144	15030	13178	14722	1000	28653	28613	28687	28712	28718
61004	28766	223	25	0	0	24	0	0	0	0	0	0	0	4729	28466	1	0	23626	1000	1000	1000	5000	2	0	8	15960	28122	28731	3	10	1000	1000	2000	28575	28568	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	2	0	13235	9695	7020	3275	10	54	21037	3272	3813	9	43	44	28235	15933	13340	15170	1000	29099	29381	29044	29171	29092
61004	28705	226	22	0	0	19	1	3	5	924	264	0	0	4907	29088	0	0	24362	1000	1000	1000	5000	2	1	0	15958	28078	28703	3	10	1000	1000	2000	28595	28689	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	0	1000	2	0	0	13009	9323	6824	3145	11	51	21205	3195	3812	10	47	45	28368	15594	13126	15158	1000	28695	28694	28808	28755	28749

Count: 8

Code:

  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]
  st1 { v0.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40059	322	1	1	0	0	0	0	0	18	0	0	1	40043	16	16	72	25	80100	100	80000	100	80000	500	1840223	40027	40049	40052	29965	3	30009	80100	200	80000	200	160000	40047	40042	1	1	80201	100	99	100	100	80000	80000	100	80074	0	36	0	0	80074	1	0	17	80002	16	36	14	0	0	0	5110	3	16	2	3	40044	1	80000	100	40053	40054	40194	40054	40061
80204	40059	322	1	0	0	1	0	0	0	19	0	0	1	40032	16	16	83	25	80100	100	80000	100	80000	500	1844537	40033	40047	40059	29972	3	30015	80100	200	80000	200	160000	40191	40048	1	1	80201	100	99	100	100	80000	80000	100	80014	0	36	0	0	80014	0	0	20	80000	16	36	14	0	0	0	5130	4	16	3	5	40039	0	80000	100	40061	40054	40052	40048	40060
80204	40053	322	1	0	0	0	0	0	0	0	0	0	1	40032	16	15	77	25	80160	100	80000	100	80000	500	1840244	40027	40059	40190	29964	107	30979	81074	204	80968	200	160000	40155	40194	1	1	80201	100	99	100	100	80000	80000	100	80134	14	36	0	0	80076	0	0	14	80002	16	37	14	3	0	0	5133	2	25	2	2	40044	0	80000	100	40198	40180	40060	40199	40193
80204	40058	324	1	0	0	0	0	0	0	3	0	0	1	40037	14	16	148	175	80100	100	80000	100	80000	500	1840197	40034	40040	40058	29971	3	30016	80100	200	80000	200	160000	40050	40042	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	0	80016	0	0	18	80002	16	36	14	0	0	0	5110	4	16	3	2	40173	0	80000	100	40054	40194	40054	40191	40187
80204	40047	322	1	0	0	0	1	0	0	19	0	0	1	40032	16	16	5	25	80100	100	80000	100	80000	500	1840244	40027	40059	40053	29960	3	30010	80100	200	80000	200	160000	40059	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	0	36	0	0	80016	1	0	23	80002	16	36	14	0	0	0	5110	3	16	4	2	40039	0	80000	100	40048	40051	40051	40051	40048
80204	40052	321	1	0	0	0	0	0	12	3	1	0	1	40044	16	16	3	25	80100	100	80000	100	80000	500	1839692	40034	40047	40048	29961	3	30008	80100	200	80000	200	160000	40052	40050	2	1	80201	100	99	100	100	80000	80000	100	80015	15	0	0	0	80016	0	1	17	80000	16	36	14	0	0	0	5110	2	16	2	2	40044	0	80000	100	40053	40043	40054	40053	40048
80204	40059	322	1	0	0	0	0	0	0	6	0	0	1	40044	16	16	0	25	80100	100	80000	100	80000	500	1840292	40022	40050	40059	29972	29	30017	80100	200	80000	200	160000	40052	40049	1	1	80201	100	99	100	100	80000	80000	100	80014	17	36	0	0	80016	0	1	19	80000	14	36	14	0	0	0	5110	2	16	2	4	40049	0	80000	100	40061	40050	40048	40048	40048
80204	40052	322	1	1	0	1	0	0	0	14	0	0	1	40313	16	16	0	25	80100	102	80000	100	80000	500	1839980	40035	40040	40061	30027	3	30142	80424	202	80484	200	160000	40194	40051	2	1	80201	100	99	100	100	80000	80000	100	80077	14	44	30	3	80016	1	0	19	80302	16	44	0	1	0	0	5110	2	16	2	2	40049	0	80000	100	40064	40053	40053	40041	40055
80204	40054	321	1	0	0	0	0	0	12	19	0	0	1	40037	16	16	4	25	80100	100	80000	100	80000	500	1840004	40017	40054	40053	29965	3	30012	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	42	0	0	80016	0	1	21	80002	16	44	14	0	0	0	5110	2	16	3	2	40051	0	80000	100	40055	40064	40053	40053	40055
80204	40053	321	0	0	0	1	0	0	12	19	0	0	1	40036	16	16	6	25	80100	100	80000	100	80000	500	1839448	40027	40043	40053	29965	3	30012	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	0	80016	1	0	19	80002	16	44	14	1	0	0	5110	3	16	3	3	40049	0	80000	100	40044	40053	40064	40055	40056

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d8	d9	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40044	310	0	0	0	0	12	3	0	0	40031	16	16	3	25	80010	10	80000	10	80000	50	1839448	40017	40366	40203	30205	3	30023	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80000	0	0	2	80002	2	42	0	5039	3	24	256	0	1	3	3	40039	80000	10	40043	40043	40043	40043	40041
80024	40043	323	0	0	0	0	0	3	0	0	40027	16	16	74	55	80070	10	80000	10	80000	50	1841989	40135	40040	40040	29975	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80062	0	0	2	80062	2	42	0	5020	5	16	0	0	3	3	3	40039	80000	10	40181	40046	40576	40044	40181
80024	40355	325	0	1	0	1	132	3	0	0	40025	16	16	0	25	80070	10	80000	10	80000	50	1844869	40018	40043	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	31	0	80002	1	0	5	80002	0	44	0	5020	3	16	0	6	0	3	3	40037	80000	10	40043	40041	40041	40041	40142
80024	40042	310	0	0	1	0	0	3	0	0	40120	0	0	28	55	80070	10	80060	10	80000	50	1841989	40017	40043	40040	29975	3	30020	80010	20	80121	20	160242	40138	40141	2	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	802	80002	2	42	0	5039	3	24	0	0	0	3	3	40040	80000	10	40044	40041	40041	40043	40043
80024	40042	311	0	0	1	2	0	0	0	0	40165	16	16	0	25	80010	10	80000	10	80000	50	1847050	40092	40043	40042	30072	3	30022	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80060	0	42	115	0	81500	1	2	11277	80062	2	42	0	5061	3	48	0	0	0	3	3	40399	80000	10	40319	40465	40702	40457	40460
80024	40461	314	1	0	0	0	0	3	0	0	40167	16	16	103	55	80130	10	80120	10	80108	50	1849258	40375	40594	40459	30255	42	30440	80442	20	80363	20	160726	40457	40464	5	1	80021	10	9	10	10	80000	80000	10	80180	4	42	59	2	80182	1	2	3001	80242	2	42	0	5168	6	48	0	0	0	3	4	40039	80000	10	40047	40186	40184	40047	40185
80024	40045	310	0	0	0	1	0	3	0	0	40027	16	16	4	25	80010	10	80000	10	80000	50	1839352	40017	40042	40043	29977	3	30023	80118	20	80000	20	160000	40042	40042	2	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	582	80002	2	0	0	5020	3	24	256	0	0	3	3	40113	80000	10	40043	40043	40044	40183	40055
80024	40042	311	0	0	1	0	0	3	0	0	40027	16	0	72	25	80010	10	80000	10	80000	50	1839472	40015	40043	40181	29981	3	30096	80118	20	80000	20	160000	40043	40142	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	29	0	80002	1	0	3	80062	0	42	0	5020	4	16	0	2	0	3	3	40042	80000	10	40041	40041	40041	40041	40044
80024	40043	310	0	0	0	0	0	88	0	1	40123	16	16	0	25	80010	10	80000	10	80000	50	1839472	40017	40040	40042	29977	3	30034	80010	20	80000	20	160000	40043	40054	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	2	2	80002	0	42	0	5020	3	16	0	2	0	3	3	40039	80000	10	40041	40041	40183	40041	40041
80024	40040	310	0	0	0	0	0	3	0	0	40031	16	16	1	25	80010	10	80060	10	80000	50	1839448	40017	40142	40042	29977	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	2	46	0	0	80062	0	2	2	80002	2	42	0	5020	3	16	0	0	0	3	3	40039	80000	10	40043	40321	40044	40043	40183

ST1 (multiple, 1 reg, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations